dsp56366 Freescale Semiconductor, Inc, dsp56366 Datasheet
dsp56366
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dsp56366 Summary of contents
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... Overview The DSP56366 supports digital audio applications requiring sound field processing, acoustic equalization, and other digital audio algorithms. The DSP56366 uses the high performance, single-clock-per-cycle DSP56300 core family of programmable CMOS digital signal processors (DSPs) combined with the audio signal processing capability of the Freescale Symphony™ DSP ...
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... EXPANSION AREA 24-BIT DSP56300 Core DDB YDB XDB PDB GDB PROGRAM PROGRAM DECODE ADDRESS CONTROLLER GENERATOR MODA/IRQA MODB/IRQB MODC/IRQC MODD/IRQD Figure 1-1 DSP56366 Block Diagram DSP56366 Technical Data, Rev. 3.1 Signal State Voltage* Asserted Deasserted Asserted Deasserted V ...
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... Sony, AC97, network and other programmable protocols The ESAI_1 shares four of the data pins with ESAI, and ESAI_1 does NOT support HCKR and HCKT (high frequency clocks) Freescale Semiconductor i : i=0 to 7). Reduces clock noise. DSP56366 Technical Data, Rev. 3.1 Overview 2 S, Sony ...
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... Documentation Table 1-1 lists the documents that provide a complete description of the DSP56366 and are required to design properly with the part. Documentation is available from a local Freescale distributor, a Freescale semiconductor sales office, a Freescale Literature Distribution Center, or through the Freescale DSP home page on the Internet (the source for the latest information). ...
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... The input and output signals of the DSP56366 are organized into functional groups, which are listed in Table 2-1 and illustrated in Figure The DSP56366 is operated from a 3.3 V supply; however, some of the inputs can tolerate special notice for this feature is added to the signal descriptions of those inputs. Table 2-1 DSP56366 Functional Signal Groupings Functional Group ...
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... OnCE™ ON-CHIP EMULATION/ DSP56366 PARALLEL HOST PORT (HDI08) Port B SERIAL AUDIO INTERFACE (ESAI) Port C SERIAL AUDIO INTERFACE(ESAI_1) Port E Port D SERIAL HOST INTERFACE (SHI) DSP56366 Technical Data, Rev. 3.1 JTAG PORT TDI TCK TDO TMS HAD(7:0) [PB0-PB7] HAS/HA0 [PB8] HA8/HA1 [PB9] HA9/HA2 [PB10] ...
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... CCP is an isolated ground for the internal processing logic. This connection must be Q connections isolated ground for sections of the address bus I/O drivers. This A connections. A DSP56366 Technical Data, Rev. 3.1 power rail. There is one V CC CCP inputs. CCS by a 0.47 μF capacitor P connection. ...
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... PINIT/NMI Input Input 2.5 External Memory Expansion Port (Port A) When the DSP56366 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-states the relevant port A signals: A0–A17, D0–D23, AA0/RAS0–AA2/RAS2, RD, WR, BB, CAS. 2-4 Table 2-3 Grounds (continued) Description is an isolated ground for sections of the data bus I/O drivers. This connection D connections ...
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... Otherwise tri-stated. Write Enable—When the DSP is the bus master active-low output that is asserted to write external memory on the data bus (D0-D23). Otherwise tri-stated. DSP56366 Technical Data, Rev. 3.1 Signal Description Signal Description 2-5 ...
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... DSP requests bus mastership deasserted when the DSP no longer needs the bus. BR may be asserted or deasserted independent of whether the DSP56366 is a bus master or a bus slave. Bus “parking” allows deasserted even though the DSP56366 is the bus master. (See the description of bus “ ...
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... Signal Description arbitration circuit when the DSP56366 becomes the next bus master. When BG is asserted, the DSP56366 must wait until BB is deasserted before taking bus mastership. When BG is deasserted, bus mastership is typically given up at the end of the current bus cycle. This may occur in the middle of an instruction that requires more than one external bus cycle for execution ...
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... RESET signal is deasserted, the initial chip operating mode is latched from the MODA, MODB, MODC, and MODD inputs. The RESET signal must be asserted during power up. A stable EXTAL signal must be supplied while RESET is being asserted. This input tolerant. DSP56366 Technical Data, Rev. 3.1 Freescale Semiconductor ...
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... HI function is selected, this signal is line 8 of the host address (HA8) input bus. GPIO Port B 9—When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input tolerant. DSP56366 Technical Data, Rev. 3.1 Signal Description 2-9 ...
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... Host Chip Select—When HDI08 is programmed to interface a nonmultiplexed host bus and the HI function is selected, this signal is the host chip select (HCS) input. The polarity of the chip select is programmable, but is configured active-low (HCS) after reset. DSP56366 Technical Data, Rev. 3.1 Signal Description Freescale Semiconductor ...
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... GPIO Port B 15—When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input tolerant. DSP56366 Technical Data, Rev. 3.1 Signal Description 2-11 ...
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... MOSI is the slave data input line when the SPI is configured as a slave. This signal is a Schmitt-trigger input when configured for the SPI Slave mode. DSP56366 Technical Data, Rev. 3 bus transactions in the I through a pull-up ...
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... This signal is tri-stated during hardware, software, personal reset, or when the HREQ1–HREQ0 bits in the HCSR are cleared. There is no need for external pull-up in this state. This input tolerant. DSP56366 Technical Data, Rev. 3 master mode Slave mode, the HA2 signal is used master mode ...
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... Port C 1—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input tolerant. DSP56366 Technical Data, Rev. 3.1 Freescale Semiconductor ...
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... Serial Data Output 5—When programmed as a transmitter, SDO5 is used to transmit data from the TX5 serial transmit shift register. Serial Data Input 0—When programmed as a receiver, SDI0 is used to receive serial data into the RX0 serial receive shift register. DSP56366 Technical Data, Rev. 3.1 2-15 ...
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... Port C 9—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. When enabled for ESAI_1 GPIO, this is the Port E 9 signal. The default state after reset is GPIO disconnected. This input tolerant. DSP56366 Technical Data, Rev. 3.1 Freescale Semiconductor ...
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... When enabled for ESAI_1 operation, this is the ESAI_1 Serial Data Output 0. Port C 11—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. When enabled for ESAI_1 GPIO, this is the Port E 11 signal. The default state after reset is GPIO disconnected. This input tolerant. DSP56366 Technical Data, Rev. 3.1 2-17 ...
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... When configured as the input flag IF0, the data value at the pin will be stored in the IF0 bit in the SAISR register, synchronized by the frame sync in normal mode or the slot in network mode. DSP56366 Technical Data, Rev. 3.1 Signal Description Freescale Semiconductor ...
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... RX1 serial receive shift register. GPIO Port E 7—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input tolerant. DSP56366 Technical Data, Rev. 3.1 Signal Description 2-19 ...
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... If TIO0 is not being used recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input but connected to Vcc through a pull-up resistor in order to ensure a stable logic level at this input. This input tolerant. DSP56366 Technical Data, Rev. 3.1 Signal Description Signal Description Freescale Semiconductor ...
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... TDO changes on the falling edge of TCK. Test Mode Select—TMS is an input signal used to sequence the test controller’s state machine. TMS is sampled on the rising edge of TCK and has an internal pull-up resistor. This input tolerant. DSP56366 Technical Data, Rev. 3.1 2-21 ...
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... NOTES DSP56366 Technical Data, Rev. 3.1 Freescale Semiconductor ...
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... Introduction The DSP56366 is a high density CMOS device with Transistor-Transistor Logic (TTL) compatible inputs and outputs. The DSP56366 specifications are preliminary and are from design simulations, and may not be fully tested or guaranteed. Finalized specifications will be published after full characterization and device qualifications are complete. ...
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... Table 3-1 Maximum Ratings (continued) Symbol STG = –40°C to +110° Table 3-2 Thermal Characteristics 1, 2 Natural Convection 3 4 Natural Convection DSP56366 Technical Data, Rev. 3 Value − +110 − +125 Symbol LQFP Value Unit or θ ° C/W θ θ ...
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... 4,5 = 6.7 mA CCI I CCW I CCS value may cause additional power consumption (DC current). To minimize ILX should be no lower than 0.9 × V IHX CC DSP56366 Technical Data, Rev. 3.1 1 Min Typ Max 3.14 3.3 3.46 2.0 — 2.0 — 3.95 CC 1.5 — 3.95 CC 0.8 × V — –0.3 — ...
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... Note 3 of the previous table. AC timing specifications, which are referenced to a device input signal, are measured in production with respect to the 50% point of the respective input signal’s transition. DSP56366 output levels are measured with the production test machine V at 0.4 V and 2.4 V, respectively. ...
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... T = internal clock cycle C 2 See the PLL and Clock Generation section in the DSP56300 Family Manual for a detailed discussion of the PLL. 3.7 EXTERNAL CLOCK OPERATION The DSP56366 system clock is an externally supplied square wave voltage source connected to EXTAL (See Figure 3-1). EXTAL V ILC Notes The midpoint is 0 ...
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... MF. CO Table 3-6 PLL Characteristics × 2/PDF CCP PCAP (MF × 580) − 100 MF × 830 MF x 1100 , for MF > DSP56366 Technical Data, Rev. 3.1 Symbol Min ET C 8. CYC 16.66 ns 8.33 ns Min Max 30 240 (MF × 780) − 140 MF × 1470 ) ...
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... T PLC × ET × PDF + (128 K − C PLC/2) × T PLC × ET × PDF + (23.75 ± C 0.5) × T (8.25 ± 0.5) × T PLC × PLC/2) × T PLC × ET × PDF + (20.5 ± 0.5) C 5.5 × T DSP56366 Technical Data, Rev. 3.1 1 (continued) Min Max 0.0 — 5.5 — 5.5 — + 2.0 37.4 — 2.0 62.4 — ...
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... L CC IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply to ). Use expression to compute maximum value and T will not be constant, and their width may vary, so timing may DSP56366 Technical Data, Rev. 3.1 1 (continued) Min Max 12T — 100 — 66 — ...
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... NMI General Purpose I/O IRQA, IRQB, IRQC, IRQD, NMI Freescale Semiconductor 9 Reset Value Figure 3-2 Reset Timing First Interrupt Instruction Execution/Fetch First Interrupt Instruction Execution 18 b) General Purpose I/O Figure 3-3 External Fast Interrupt Timing DSP56366 Technical Data, Rev. 3 First Fetch AA0460 3-9 ...
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... MODA, MODB, MODC, MODD, PINIT IRQA A0–A17 Figure 3-6 Recovery from Stop State Using IRQA 3- Figure 3-5 Operating Mode Select Timing 24 25 DSP56366 Technical Data, Rev. 3.1 AA0463 IRQA, IRQB IRQD, NMI V IL AA0465 First Instruction Fetch AA0466 Freescale Semiconductor ...
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... Freescale Semiconductor 26 25 DMA Source Address 29 First Interrupt Instruction Execution Symbol Expression ( × ( × × T DSP56366 Technical Data, Rev. 3.1 First IRQA Interrupt Instruction Fetch AA0467 AA1104 1 2 Min Max − 4.0 12.0 — ≤ WS ≤ 3] − 4.0 46.0 — ...
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... All frequencies: 1.25 × ≤ WS ≤ 7] 2.25 × T (WS + 0.75) × (WS + 0.25) × OHZ (WS + 0.75) × (WS − 0.25) × DSP56366 Technical Data, Rev. 3.1 1 (continued) 2 Min Max − 2.0 0.1 — − 2.0 8.4 — C [WS ≥ 4] − 4.0 [ 8.5 — C 12.7 — − 4.0 C − ...
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... WS ≤ 7] 2.25 × T [WS ≥ 8] 1.25 × T — [1 ≤ WS ≤ 3] 2.25 × ≤ WS ≤ 7] 3.25 × T [WS ≥ 8] 0.75 × ≤ WS ≤ 3] 1.75 × ≤ WS ≤ 7] 2.75 × T [WS ≥ 8] DSP56366 Technical Data, Rev. 3.1 (continued) 2 Min Max Unit − 2.0 0.1 — − 2.0 8.4 — − 2.0 16.7 — ...
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... ≤ WS ≤ 3] 2.5 × ≤ WS ≤ 7] 3.5 × T [WS ≥ 8] 0.5 × T (WS + 0.25) × T 0.25 × ≤ WS ≤ 3] 1.25 × ≤ WS ≤ 7] 2.25 × T [WS ≥ 8] 0.25 × DSP56366 Technical Data, Rev. 3.1 (continued) 2 Min Max Unit − 4.0 0.2 — C 6.3 — − 4.0 16.8 — C − 4.0 25.2 — ...
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... D0–D23 Freescale Semiconductor 100 113 116 115 105 104 119 Figure 3-9 SRAM Read Access 100 107 101 102 114 108 Figure 3-10 SRAM Write Access DSP56366 Technical Data, Rev. 3.1 117 106 118 Data In AA0468 103 118 119 109 Data Out 3-15 ...
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... Figure 3-14 should be used for primary selection only. Notes This figure should be use for primary selection. For exact and detailed timings see the following tables. 120 66 80 100 3 Wait States 4 Wait States DSP56366 Technical Data, Rev. 3.1 Chip Frequency (MHz) AA0472 Freescale Semiconductor ...
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... RCH C 0.5 × T − 4.2 t WCH C 1.5 × T − 4 1.75 × T − 4.3 t RWL C 1.75 × T − 4.3 t CWL C 0.25 × T − 4 DSP56366 Technical Data, Rev. 3 MHz 30 MHz Unit Min Max Min Max 100.0 — 66.7 — 62.5 — 41.7 — — 42.5 — 25.8 — 67.5 — 42.5 0.0 — ...
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... T t CAC C 1.5 × 2.5 × 2.5 × OFF 1.75 × RSH C 3.25 × RHCP C 1.5 × CAS C DSP56366 Technical Data, Rev. 3 (continued MHz 30 MHz Min Max Min Max 33.5 — 21.0 — 45.7 — 29.0 — 71.0 — 46.0 — — 42.5 — ...
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... The number of wait states for Page mode access is specified in the DCR. 2 The refresh period is specified in the DCR. 3 The asynchronous delays specified in the expressions are valid for DSP56366. 4 There are no DRAMs fast enough to fit to two wait states Page mode @ 100MHz (See Freescale Semiconductor ...
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... RHCP t CAS 5 t CRP ASC t CAH t RAL t RCS t RCH t WCH RWL t CWL t DS DSP56366 Technical Data, Rev. 3.1 equals 3 × T for PC C and not t OFF GZ Expression Min Max Unit 2 × T 40.0 — 1.25 × T 35.0 — × T − 7.0 — 13 × ...
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... The number of wait states for Page mode access is specified in the DCR. 2 The refresh period is specified in the DCR. 3 The asynchronous delays specified in the expressions are valid for DSP56366. 4 All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t read-after-read or write-after-write sequences). ...
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... RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t 3-22 Symbol t ASC t CAH t RAL t RCS t RCH t WCH RWL t CWL WCS t ROH DSP56366 DSP56366 Technical Data, Rev. 3 (continued) 4 Expression Min Max − 4.0 T 4.3 — C 3.5 × T − 4.0 25.2 — × T − 4.0 37.7 — C 1.25 × T − 4.0 6.4 — C 1.25 × T − 4.0 6.4 — ...
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... Figure 3-12 DRAM Page Mode Write Accesses Freescale Semiconductor 131 137 139 140 141 Column Column Address Address 151 144 145 146 155 150 149 Data Out Data Out DSP56366 Technical Data, Rev. 3.1 136 135 138 142 Last Column Address 143 147 148 156 Data Out AA0473 3-23 ...
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... RD D0–D23 Figure 3-13 DRAM Page Mode Read Accesses 3-24 131 137 139 140 141 Column Column Address Address 143 133 153 Data In Data In DSP56366 Technical Data, Rev. 3.1 136 135 138 142 Last Column Address 132 152 134 154 Data In AA0474 Freescale Semiconductor ...
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... C 1.25 × CAC C 1.5 × OFF 1.75 × 3.25 × RAS C 1.75 × RSH C DSP56366 Technical Data, Rev. 3.1 Chip Frequency (MHz) AA0475 MHz 30 MHz Min Max Min Max 250.0 — 166.7 — C − 7.5 — 130.0 — 84.2 − 7.5 — ...
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... C 2.25 × 1.75 × 3.25 × DHR C 3 × T − 4.3 t WCS C 0.5 × CSR C 1.25 × RPC C DSP56366 Technical Data, Rev. 3 (continued MHz 30 MHz Min Max Min Max − 4.0 133.5 — 87.7 — − 4.0 58.5 — 37.7 — ± 2 73.0 77.0 48.0 52.0 ± ...
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... RP 5.75 × RAS 3.25 × RSH 4.75 × CSH 2.25 × CAS 2.5 × RCD 1.75 × RAD DSP56366 Technical Data, Rev. 3 (continued MHz 30 MHz Min Max Min Max − 4.0 221.0 — 146.0 — — 192.5 — 125.8 0.0 — ...
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... 5.75 × DHR 5.5 × WCS C 1.5 × CSR C 1.75 × RPC 8.5 × ROH C 7.5 × 7.5 × DSP56366 Technical Data, Rev. 3 (continued) 66 MHz 80 MHz 4 Min Max Min Max − 4.0 59.8 — 49.1 C − 4.0 37.7 — 30.4 C − 4.0 45.2 — 36.6 C − 4.0 22.5 — ...
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... The number of wait states for out-of-page access is specified in the DCR. 2 The refresh period is specified in the DCR deassertion will always occur after CAS deassertion; therefore, the restricted timing The asynchronous delays specified in the expressions are valid for DSP56366. 5 Either must be satisfied for read cycles. RCH ...
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... The number of wait states for out-of-page access is specified in the DCR. 2 The refresh period is specified in the DCR deassertion will always occur after CAS deassertion; therefore, the restricted timing The asynchronous delays specified in the expressions are valid for DSP56366. 5 Either must be satisfied for read cycles. RCH ...
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... CRP ASR t RAH t ASC t CAH RAL t RCS t RCH t RRH t WCH t WCR t WP 15.75 × RWL DSP56366 Technical Data, Rev. 3 Expression Min Max 16 × T 133.3 — C 8.25 × T − 5.7 — 63.0 C 4.75 × T − 5.7 — 33.9 C 5.5 × T − 5.7 — 40.1 C 0.0 0.0 — 6.25 × T − 4.0 48.1 — ...
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... RCH RRH 3-32 3 Symbol t CWL DHR t WCS t CSR t RPC t ROH DSP56366 Technical Data, Rev. 3 (continued) Expression Min Max 14.25 × T − 4.3 114.4 — C 8.75 × T − 4.0 68.9 — C 6.25 × T − 4.0 48.1 — C 9.75 × T − 4.0 77.2 — C 9.5 × T − ...
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... Figure 3-15 DRAM Out-of-Page Read Access Freescale Semiconductor 157 163 165 167 164 168 170 166 171 173 175 Row Address Column Address 172 176 177 191 160 159 158 192 DSP56366 Technical Data, Rev. 3.1 162 174 179 168 193 161 Data In AA0476 3-33 ...
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... Figure 3-16 DRAM Out-of-Page Write Access 3-34 157 163 165 167 164 168 166 170 171 173 172 176 Row Address Column Address 181 175 188 180 182 184 183 187 186 185 194 Data Out DSP56366 Technical Data, Rev. 3.1 162 174 195 AA0477 Freescale Semiconductor ...
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... Freescale Semiconductor 157 163 162 165 189 Figure 3-17 DRAM Refresh Access Expression 2 . Table 3-17 Figure 3-18 . DSP56366 Technical Data, Rev. 3.1 162 AA0478 120 MHz Min Max — 25.8 21.7 — is required. BG inputs to different 56300 devices (on the Unit ...
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... BG asserted, and BB negated, may cause another 56300 component to assume mastership at the same time. Therefore some non-overlap period between one BG input active to another BG input active is required. Timing 251 ensures that such a situation is avoided. 3-36 250 250+251 DSP56366 Technical Data, Rev. 3.1 251 Freescale Semiconductor ...
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... HCS assertion to output data valid Freescale Semiconductor 3 Characteristics after “Last Data Register” reads DSP56366 Technical Data, Rev. 3 120 MHz Expression Min Max T + 9.9 18.3 — C — 9.9 — 5,6 2.5 × 6.6 27.4 — C — 13.2 — ...
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... Delay from DMA HACK assertion to HOREQ deassertion for “Last Data Register” read or write • HROD = 1, open drain Host Request 1 See Host Port Usage Considerations in the DSP56366 User’s Manual the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable. = 3.3 V ± 0. ...
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... HRD, HDS HD0–HD7 HOREQ, HRRQ, HTRQ Figure 3-21 Read Timing Diagram, Non-Multiplexed Bus Freescale Semiconductor 317 327 329 326 336 337 333 330 317 318 328 332 319 327 329 326 340 341 DSP56366 Technical Data, Rev. 3.1 318 328 AA1105 338 AA0484 3-39 ...
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... HA0–HA2 HCS HWR, HDS HD0–HD7 HOREQ, HRRQ, HTRQ Figure 3-22 Write Timing Diagram, Non-Multiplexed Bus 3-40 336 331 320 321 324 340 341 DSP56366 Technical Data, Rev. 3.1 337 333 325 339 AA0485 Freescale Semiconductor ...
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... HA8–HA10 322 HAS HRD, HDS HAD0–HAD7 HOREQ, HRRQ, HTRQ Figure 3-23 Read Timing Diagram, Multiplexed Bus Freescale Semiconductor 336 337 323 317 334 335 327 328 329 Address Data 326 340 341 DSP56366 Technical Data, Rev. 3.1 318 319 338 AA0486 3-41 ...
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... HACK (Input) H0–H7 (Input) Figure 3-25 Host DMA Write Timing Diagram 3-42 336 323 320 334 324 335 Data Address 340 341 342 343 344 320 321 TXH/M/L Write 324 325 Data Valid DSP56366 Technical Data, Rev. 3.1 321 325 339 AA0487 Freescale Semiconductor ...
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... Mode Mode — Bypassed Narrow Wide (min) Master Bypassed SPICC Narrow Wide Master Bypassed Narrow Wide Slave Bypassed Narrow Wide DSP56366 Technical Data, Rev. 3.1 342 318 328 329 Expression Min Max — — 0 — — 50 — — 100 6×T +46 96 — ...
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... Narrow Wide Slave Bypassed Narrow Wide Master/Slave Bypassed Narrow MAX{(20-T Wide MAX{(40-T Master/Slave Bypassed Narrow Wide Slave — 2 Slave — DSP56366 Technical Data, Rev. 3.1 Expression Min Max 0.5×t –10 38 — SPICC 0.5×t –10 91 — SPICC 0.5×t –10 126.5 — SPICC 2.5×T +12 32.8 — ...
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... Slave Bypassed Narrow Wide Slave Bypassed Narrow Wide Slave — Slave — Master Bypassed Narrow Wide Master — Master — DSP56366 Technical Data, Rev. 3.1 Expression Min Max 2×T +33 — 49.7 C 2×T +123 — 139.7 C 2×T +210 — 226 13.3 — ...
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... MISO (Input) MOSI (Output) 161 HREQ (Input) 3-46 143 142 144 142 144 143 148 149 MSB Valid 152 MSB 163 Figure 3-27 SPI Master Timing (CPHA = 0) DSP56366 Technical Data, Rev. 3.1 141 144 141 144 149 LSB Valid 153 LSB AA0271 Freescale Semiconductor ...
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... MOSI (Output) 161 HREQ (Input) Freescale Semiconductor 143 142 144 142 144 143 148 149 MSB Valid 152 MSB 162 163 Figure 3-28 SPI Master Timing (CPHA = 1) DSP56366 Technical Data, Rev. 3.1 141 144 141 144 148 149 LSB Valid 153 LSB AA0272 3-47 ...
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... HREQ (Output) 3-48 143 142 144 142 144 143 152 153 153 MSB 148 149 MSB Valid 157 Figure 3-29 SPI Slave Timing (CPHA = 0) DSP56366 Technical Data, Rev. 3.1 141 147 144 160 141 144 151 LSB 149 LSB Valid 159 AA0273 Freescale Semiconductor ...
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... HREQ (Output) Freescale Semiconductor 143 142 144 142 144 143 152 152 MSB 148 149 MSB Valid 157 Figure 3-30 SPI Slave Timing (CPHA = 1) DSP56366 Technical Data, Rev. 3.1 141 147 144 144 153 151 LSB 148 149 LSB Valid 158 AA0274 3-49 ...
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... HD;STA T 4.7 LOW T 4.0 HIGH T R — — T 250 SU;DAT T 0.0 HD;DAT F DSP 10.6 11.8 13.1 T — VD;DAT T 4.0 SU;STO t 0.0 SU;RQI DSP56366 Technical Data, Rev. 3.1 5 Fast Mode 4 Max Min Max 0 — — 50 100 — 100 100 — 400 — 2.5 — — 1.3 — — 0.6 — — 0.6 — ...
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... CCP 4440 — × 0 4373 — 4373 — t 0.0 — HO;RQI 2 C Standard Mode Fast Mode. DSP56366 Technical Data, Rev. 3.1 5 Fast Mode Unit Min Max ns — 46.7 — 136.7 — 224.7 ns 46.7 — 96.7 — 151.6 — ns 1041 — 999 — 958 — ...
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... CCP + 2 8.33ns), operating in a standard mode 1000ns), with wide filters enabled: R × 10μs 2.5 8.33ns – – 223ns 1000ns [ ] ⁄ × = 8756ns 8.33ns DSP56366 Technical Data, Rev. 3.1 ( × HRS – and the filters selected should be chosen Table 3-21. × ...
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... CCP 171 176 175 180 178 179 MSB LSB 186 182 189 184 2 Figure 3- Timing DSP56366 Technical Data, Rev. 3 × HRS ) – × – 8796.48ns ACK Stop 183 187 AA0275 3-53 ...
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... T C — — — — 6 — — 6 — — — — — — — — — — — — — — — — DSP56366 Technical Data, Rev. 3.1 4 Min Max Condition Unit 33.3 — 25.0 — 27.2 — 6.7 — 12.5 — ns 6.7 — 12.5 — ...
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... T C — 21.0 — — — — — — — — — — DSP56366 Technical Data, Rev. 3.1 4 Min Max Condition Unit 0.0 — 19.0 — 6.0 — 0.0 — — 29 — ...
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... Periodically sampled and not 100% tested 3-56 Symbol Expression — — — — — — — — — — — — DSP56366 Technical Data, Rev. 3.1 4 Min Max Condition Unit 2.0 — 21.0 — 4.0 — 0.0 — — ...
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... In normal mode, the output flag state is asserted for the entire frame period. Freescale Semiconductor 430 432 446 447 450 454 454 452 First Bit 459 453 461 458 461 460 462 Figure 3-32 ESAI Transmitter Timing DSP56366 Technical Data, Rev. 3.1 451 455 Last Bit 456 See Note AA0490 3-57 ...
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... FSR (Word) In Flags In HCKT SCKT(output) 3-58 430 431 432 433 434 437 439 First Bit 441 443 442 444 Figure 3-33 ESAI Receiver Timing 463 464 Figure 3-34 ESAI HCKT Timing DSP56366 Technical Data, Rev. 3.1 438 440 Last Bit 443 445 AA0491 Freescale Semiconductor ...
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... ACI low duration 223 ACI rising edge to ADO valid Note: In order to assure proper operation of the DAX, the ACI frequency should be less than 1/2 of the DSP56366 internal clock frequency. For example, if the DSP56366 is running at 120 MHz internally, the ACI frequency should be less than 60 MHz. ...
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... Valid only when PLL enabled with multiplication factor equal to one. 3-60 Table 3-24 Timer Timing Expression 2 × 2 × 2 480 481 Table 3-25 GPIO Timing 1 Expression 6.75 × DSP56366 Technical Data, Rev. 3.1 120 MHz Unit Min Max 18.7 — ns 18.7 — ns AA0492 Min Max — 32.8 4.8 — 10.2 — ...
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... TCK low to output high impedance 508 TMS, TDI data setup time Freescale Semiconductor 492 493 Valid 494 495 496 Figure 3-38 GPIO Timing Table 3-26 JTAG Timing Characteristics × 3); maximum 22 MHz) C DSP56366 Technical Data, Rev. 3.1 490 491 1, 2 All frequencies Min Max 0.0 22.0 45.0 — 20.0 — 0.0 3.0 5.0 — ...
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... Table 3-26 JTAG Timing (continued) Characteristics = 501 502 VM VIL 504 Input Data Valid 506 Output Data Valid 507 506 Output Data Valid DSP56366 Technical Data, Rev. 3.1 All frequencies Min Max 25.0 — 0.0 44.0 0.0 44.0 502 VM 503 AA0496 VIH 505 AA0497 Freescale Semiconductor Unit ...
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... TCK VIL (Input) TDI TMS (Input) TDO (Output) TDO (Output) TDO (Output) Figure 3-41 Test Access Port Timing Diagram Freescale Semiconductor 508 Input Data Valid 510 Output Data Valid 511 510 Output Data Valid DSP56366 Technical Data, Rev. 3.1 VIH 509 AA0498 3-63 ...
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... NOTES DSP56366 Technical Data, Rev. 3.1 Freescale Semiconductor ...
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... Pin-out and Package Information This section provides information about the available package for this product, including diagrams of the package pinouts and tables describing how the signals described in Descriptions” 1 are allocated for the package. The DSP56366 is available in a 144-pin LQFP package. Table 4-1 and Table 4-2 show the pin/name assignments for the packages ...
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... HRW/HRD 22 HACK/HRRQ 23 HOREQ/HTRQ 24 VCCS 25 GNDS 26 ADO 27 ACI 28 TIO0 29 HCS/HA10 30 HA9/HA2 31 HA8/HA1 32 HAS/HA0 33 HAD7 34 HAD6 35 HAD5 36 4-2 Figure 4-1 144-pin package DSP56366 Technical Data, Rev. 3.1 108 D6 107 D5 106 D4 105 D3 104 GNDD 103 VCCD 102 D2 101 D1 100 D0 99 A17 98 A16 97 A15 96 GNDA 95 VCCQH 94 A14 93 A13 ...
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... PCAP 46 120 PINIT/NMI# 61 130 RD RESET SCK/SCL 19 SCKR 15 54 SCKR_1 60 90 SCKT 14 127 SCKT_1 53 DSP56366 Technical Data, Rev. 3.1 Signal Name 9 SDO0/SDO0_1 SDO1/SDO1_1 SDO2/SDI3/SDO2_1/SDI3_1 SDO3/SDI2/SDO3_1/SDI2_1 SDO4/SDI1 SDO4_1/SDI1_1 SDO5/SDI0 SDO5_1/SDI0_1 SS#/HA2 TA# TCK TDI TDO TIO0 TMS VCCA VCCA VCCA VCCC 3 VCCC VCCD ...
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... VCCC 101 66 GNDC 102 67 WR# 103 68 RD# 104 69 AA1 105 70 AA0 106 71 BG# 107 72 A0 108 DSP56366 Technical Data, Rev. 3.1 Signal Name Pin No. Signal Name A1 109 D7 VCCA 110 D8 GNDA 111 VCCD A2 112 GNDD A3 113 D9 A4 114 D10 A5 115 D11 VCCA ...
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... LQFP Package Mechanical Drawing Figure 4-2 DSP56366 144-pin LQFP Package Freescale Semiconductor CASE 918-03 DSP56366 Technical Data, Rev. 3.1 4-5 ...
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... DSP56366 Technical Data, Rev. 3.1 Freescale Semiconductor ...
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... Freescale Semiconductor , in °C can be obtained from the following equation × θ θJA θJC θCA . For example, the user can change the air flow around θCA θJA DSP56366 Technical Data, Rev. 3.1 do not satisfactorily answer whether 5-1 ...
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... TDI, TCK). 5 determined by a thermocouple, the thermal resistance T CAUTION ). The suggested value for a pullup or pulldown resistor CC power source to GND. CC and GND circuits. CC DSP56366 Technical Data, Rev. 3.1 – has been defined JT pin on the DSP and from CC and GND ...
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... Take special care to minimize noise levels on the V • If multiple DSP56366 devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices. • RESET must be asserted when the chip is powered up. A stable EXTAL signal must be supplied while RESET is being asserted. • ...
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... The phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed values. 5-4 ⁄ MHz = – I typF2 typF1 NOTE DSP56366 Technical Data, Rev. 3.1 ) ⁄ Freescale Semiconductor ...
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... HC bit is cleared. • Variance in the Host Interface Timing—The host interface (HDI) may vary (e.g. due to the PLL lock time at reset). Therefore, a host which attempts to load (bootstrap) the DSP should first make Freescale Semiconductor DSP56366 Technical Data, Rev. 3.1 5-5 ...
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... HF0 and HF1 as an encoded pair, (i.e., the four combinations 00, 01, 10, and 11 each have significance). A very small probability exists that the DSP will read the status bits synchronized during transition. Therefore, HF0 and HF1 should be read twice and checked for consensus. 5-6 DSP56366 Technical Data, Rev. 3.1 Freescale Semiconductor ...
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... Ordering Information Consult a Freescale Semiconductor, Inc. sales office or authorized distributor to determine product availability and to place an order. For information on ordering DSP Audio products, refer to the current SG1004, DSP Selector Guide, at http://www.freescale.com Freescale Semiconductor DSP56366 Technical Data, Rev. 3.1 6-1 ...
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... NOTES DSP56366 Technical Data, Rev. 3.1 Freescale Semiconductor ...
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... Freescale Semiconductor 200,55,0,0,0 ; Interrupt vectors for program debug only ; MAIN (external) program starting address ; INTERNAL X-data memory starting address ; INTERNAL Y-data memory starting address P:START #$0d0000,x:M_PCTL ; PLL enable ; CLKOUT disable #INT_PROG,r0 #PROG_START,r1 #(PROG_END-PROG_START),PLOAD_LOOP p:(r1)+,x0 x0,p:(r0)+ #INT_XDAT,r0 DSP56366 Technical Data, Rev. 3.1 ; XTAL disable A-1 ...
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... PROG_END nop nop XDAT_START ; org A-2 #XDAT_START,r1 #(XDAT_END-XDAT_START),XLOAD_LOOP p:(r1)+,x0 x0,x:(r0)+ #INT_YDAT,r0 #YDAT_START,r1 #(YDAT_END-YDAT_START),YLOAD_LOOP p:(r1)+,x0 x0,y:(r0)+ INT_PROG #$0,r0 #$0,r4 #$3f,m0 #$3f, #$0,x0 #$0,x1 #$0,y0 #$0,y1 #4,omr ; ebd #60,_end x0,y0,a x:(r0)+,x1 x1,y1,a x:(r0)+,x0 a,b x0,y0,a x:(r0)+,x1 x1,y1,a b1,x:$ff sbr x:0 $262EB9 $86F2FE $E56A5F DSP56366 Technical Data, Rev. 3.1 y:(r4)+,y1 y:(r4)+,y0 y:(r4)+,y0 Freescale Semiconductor ...
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... DSP56366 Technical Data, Rev. 3.1 A-3 ...
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... DSP56366 Technical Data, Rev. 3.1 Freescale Semiconductor ...
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... YDAT_END Freescale Semiconductor $ADF7BF $4B3E8C $6079D5 $E0F5EA $8230DB $A3B778 $2BFE51 $E0A6B6 $68FFB7 $28F324 $8F2E8D $667842 $83E053 $A1FD90 $6B2689 $85B68E $622EAF $6162BC $E4A245 DSP56366 Technical Data, Rev. 3.1 A-5 ...
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... For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Document Number: DSP56366 Rev. 3.1 1/2007 NOTES Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...