adsp-bf527c Analog Devices, Inc., adsp-bf527c Datasheet - Page 36
adsp-bf527c
Manufacturer Part Number
adsp-bf527c
Description
Blackfin Embedded Processor
Manufacturer
Analog Devices, Inc.
Datasheet
1.ADSP-BF527C.pdf
(44 pages)
- Current page: 36 of 44
- Download datasheet (3Mb)
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
DIGITAL AUDIO INTERFACE—SLAVE MODE
Table 35. Digital Audio Data Timing—Slave Mode
1
Parameter
t
t
t
t
t
t
t
t
AVDD, HPVDD, V
BCY
BCH
BCL
LRSU
LRH
DS
DH
DD
CODEC_BCLK
DACLRC/
ADCLRC
DACDAT
ADCDAT
CODEC_BCLK cycle time
CODEC_BCLK pulse width high
CODEC_BCLK pulse width low
DACLRC/ADCLRC set-up time to CODEC_BCLK rising
edge
DACLRC/ADCLRC hold time from CODEC_BCLK
rising edge
DACDAT set-up time to CODEC_BCLK rising edge
DACDAT hold time from CODEC_BCLK rising edge
ADCDAT propagation delay from CODEC_BCLK
falling edge
DDEXT
= 3.3 V, AGND = 0 V, T
t BCH
A
t BCY
= +25°C, Slave Mode, f
t DD
Figure 32. Digital Audio Data Timing—Slave Mode
Rev. PrC | Page 36 of 44 | June 2008
t BCL
t
DS
Test Conditions
S
= 48 kHz, XTI/CODEC_MCLK = 256 × f
t LRH
t DH
1
t LRSU
Preliminary Technical Data
S
unless otherwise stated.
20
10
10
Min Typical Max Unit
50
20
10
10
0
10
ns
ns
ns
ns
ns
ns
ns
ns
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