adsp-bf527c Analog Devices, Inc., adsp-bf527c Datasheet - Page 16

• Manufacturer Part Number: adsp-bf527c
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
CODEC OPERATION
This section describes various operating modes for the CODEC.
CODEC RESETTING
The CODEC contains a power-on reset circuit that resets the
internal state of the device to a known condition. The power-on
reset is applied as V
voltage level of V
V
power-on reset is re-applied. The threshold voltages and associ-
ated hysteresis are shown in the
Page
The programmer also has the ability to reset the device to a
known state using the software control shown in
In SPI mode the software reset is applied on the rising edge of
CSB and released on the next rising edge of CSCL. In TWI
mode the reset is applied for the duration of the ACK signal
(approximately one CSCL period) as shown in
Page
Table 11. Software Control of Reset
Minimizing Pop Noise At The Analog Outputs
Follow these procedures to minimize popping or click noises
when the system is powered up or down.
Power Up Sequence
Power Down Sequence
CLOCKING
In a typical digital audio system there is only one central clock
source producing a reference clock to which all audio data pro-
cessing is synchronized. This clock is often referred to as the
audio system master clock. The CODEC is capable of either
generating this system clock or receiving it from an external
source.
Register
Address
000 1111 8:0 RESET Not Reset Reset Register
DDEXT
1. Switch on power supplies. By default the CODEC is in
2. Set all required bits in the power down register 6 to ‘0’;
3. Set the required values in all other registers except for the
4. Set the ACTIVE bit in register 9.
5. The last write of the sequence should set OUTPD to ‘0’
1. Set the OUTPD bit to ‘1’ (power down).
2. Remove the CODEC supplies.
standby mode, the DAC is digitally muted, and the audio
interface and outputs are all off.
except the OUTPD bit which should be set to ‘1’ (default).
ACTIVE bit in register 9.
(active) in register 6. This enables the DAC signal path, free
of significant power-up noise.
32.
25.
later falls below a minimum turn-on threshold, the
Bit Label Default
DDEXT
DDEXT
crosses a minimum turn-off threshold. If
powers on and released only after the
Electrical Characteristics on
Description
00000000 resets the CODEC
Figure 27 on
Table
Rev. PrC | Page 16 of 44 | June 2008
11.
In applications where the CODEC is the system clock source, a
suitable crystal is connected between the XTI/CODEC_MCLK
input and XTO output pins as shown in
For applications where the external system generates the refer-
ence clock, the external clock can be applied directly through
the XTI/CODEC_MCLK input pin. No software configuration
is necessary. In this situation, the oscillator circuit of the
CODEC can be safely powered down to conserve power (see
Power Down Modes on Page
CODEC Clock
The CODEC can be clocked either by CODEC_MCLK or
CODEC_MCLK divided by 2. This is controlled by software as
shown in
Table 12. Software Control of CODEC Clock
Having a programmable CODEC_MCLK divider allows the
device to be used in applications where higher frequency master
clocks are available. For example the CODEC can support a
master clock of 512 × f
Crystal Oscillator
The CODEC includes a crystal oscillator circuit that allows the
audio system reference clock to be generated on the CODEC.
An external crystal is connected to the CODEC as shown in
Figure
for low EMI.
The CODEC crystal oscillator provides an extremely low jitter
clock. Low jitter clocks are a requirement for high quality audio
ADC and DACs. The CODEC architecture is less susceptible
than most converter techniques, but still requires clocks with
less than approximately 1 ns of jitter. In applications where
Register
Address
000 1000 6
18. The crystal oscillator is a low radiation type designed
Table
Bit Label
CLKIDIV2 0
12.
C
XTI/CODEC_MCLK
Figure 18. Crystal Connection
P
Preliminary Technical Data
GND
S
while operating in a 256 × f
Default Description
25).
CODEC Clock Divider Select
1 = CODEC Clock is
CODEC_MCLK ÷ 2
0 = CODEC Clock is
CODEC_MCLK
C
P
GND
Figure
XTO
18.
S
mode.