cs5461 Cirrus Logic, Inc., cs5461 Datasheet - Page 33

• Manufacturer Part Number: cs5461
• Description: Single-phase, Bidirectional Power/energy Ic
• Manufacturer: Cirrus Logic, Inc.

7. REGISTER DESCRIPTION
7.1 Configuration Register
DS546F2
1. “Default**” => bit status after power-on or reset
2. Any bit not labeled is Reserved. A zero should always be used when writing to one of these bits.
PC[6:0]
Igain
EWA
Address: 0
Default** = 0x000001
[IMODE IINV] Soft interrupt configuration bits. Select the desired pin behavior for indication of an interrupt.
EPP
EOP
EDP
VHPF
IHPF
EWA
PC6
23
15
7
VHPF
PC5
22
14
When MCLK=4.096 MHz and K=1, the phase adjustment range is about -2.8 to +2.8 degrees
and each step is about 0.04 degrees (assuming a power line frequency of 60 Hz). If (MCLK / K)
is not 4.096 MHz, the values for the range and step size should be scaled by the factor
4.096MHz / (MCLK / K).
0 = gain is 10 (default)
1 = gain is 50
0 = normal outputs (default)
10 = falling edge (INT is normally high)
also be accessed using the Status Register.
1 = EOP and EDP bits control the EOUT and EDIR pins.
Default = '0'
0 = High-pass filter disabled (default)
1 = High-pass filter enabled
Phase compensation. A 2’s complement number which sets the delay in the voltage channel.
Default setting is 0000000 = 0.0215 degrees phase delay at 60 Hz (when MCLK = 4.096 MHz).
Sets the gain of the current PGA
Allows the EOUT and EDIR pins to be configured as open-collector output pins.
1 = only the pull-down device of the EOUT and EDIR pins are active
00 = active low level (default)
01 = active high level
11 = rising edge (INT is normally low)
Allows the EOUT and EDIR pins to be controlled by the DL0 and DL1 bits. EOUT and EDIR can
0 = Normal operation of the EOUT and EDIR pins. (default)
When EPP = 1, EOUT becomes a user defined pin, and EOP sets the value of the EOUT pin.
When EPP = 1, EDIR becomes a user defined pin, EDP sets the value of the EDIR pin.
Default = '0'
Control the use of the High Pass Filter on the voltage Channel.
Control the use of the High Pass Filter on the Current Channel.
6
IHPF
PC4
21
13
5
IMODE
iCPU
PC3
20
12
4
PC2
IINV
K3
19
11
3
PC1
EPP
K2
18
10
2
EOP
PC0
K1
17
9
1
CS5461
Igain
EDP
K0
16
8
0
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