cs5461 Cirrus Logic, Inc., cs5461 Datasheet
cs5461
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cs5461 Summary of contents
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... VIN- VREFIN VREFOUT http://www.cirrus.com Description The CS5461 is an integrated power measure- ment device which combines two ∆Σ ADCs, high speed power calculation functions, and a serial interface on a single chip designed to accu- rately measure Instantaneous Current and Voltage, and calculate: Instantaneous Power, ...
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... Theory of Operation ......................................................................................................... 13 3.1.1 High-Rate Digital Low-Pass Filters ..................................................................... 15 3.1.2 Digital Compensation Filters ............................................................................... 15 3.1.3 Digital High-Pass Filters ...................................................................................... 15 3.1.4 Gain and DC Offset Adjustment .......................................................................... 15 3.1.5 Average (Real) Power Computation ................................................................... 15 3.1.6 RMS Computations ............................................................................................. 16 3.2 Performing Measurements ............................................................................................... 16 3.3 CS5461 Linearity Performance ........................................................................................ 16 4. FUNCTIONAL DESCRIPTION ............................................................................................... 17 4.1 Analog Inputs ................................................................................................................... 17 4.2 Voltage Reference ........................................................................................................... 17 4.3 Oscillator Characteristics ................................................................................................. 17 4.4 Calibration ........................................................................................................................ 18 4.4.1 Overview of Calibration Process ......................................................................... 18 4.4.2 Calibration Sequence .......................................................................................... 18 4 ...
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... SERIAL PORT OVERVIEW .................................................................................................... 29 6.1 Commands ...................................................................................................................... 29 6.2 Serial Port Interface ......................................................................................................... 32 6.3 Serial Read and Write ..................................................................................................... 32 6.4 System Initialization ......................................................................................................... 32 6.5 Serial Port Initialization .................................................................................................... 32 6.6 CS5461 Power States ..................................................................................................... 33 7. REGISTER DESCRIPTION .................................................................................................... 34 7.1 Configuration Register ...................................................................................................... 34 7.2 DC Current Offset Register and DC Voltage Offset Register ........................................... 35 7.3 AC/DC Current Gain Register and AC/DC Voltage Gain Register ................................... 35 7.4 Cycle Count Register........................................................................................................ 35 7.5 PulseRateE Register ........................................................................................................ 36 7 & ...
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... LIST OF FIGURES Figure 1. CS5461 Read and Write Timing Diagrams .................................................................... 13 Figure 2. Data Flow. ...................................................................................................................... 14 Figure 3. Oscillator Connection ..................................................................................................... 17 Figure 4. System Calibration of Gain. ........................................................................................... 18 Figure 5. System Calibration of Offset. ......................................................................................... 18 Figure 6. Calibration Data Flow..................................................................................................... 19 Figure 7. Example of AC Gain Calibration .................................................................................... 20 Figure 8. Another Example of AC Gain Calibration....................................................................... 20 Figure 9. Example of DC Gain Calibration .................................................................................... 20 Figure 10 ...
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... V or above +5 V. The CS5461 includes two high-rate digital filters, which decimate the output from the two ∆Σ modulators. These filters integrate the output of the ∆Σ modulators for both channels to yield instantaneous voltage and current waveform output data at a (MCLK/K)/1024 output word rate (OWR) ...
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... CS - When low, the port will recognize SCLK. An active high on this pin forces the SDO pin to a high impedance state. MODE - When at logic high, the CS5461 will operate in auto-boot mode. For normal operation this pin must be left unconnected. FOUT - Issues active-low pulses, such that the number of pulses is proportional to the measured real energy ...
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... PFMON - The power fail Monitor pin monitors the analog supply. Typical threshold level (PMLO) is 2.45 V with respect to the VA- pin. If PFMON voltage threshold is tripped, the LSD (low-supply detect) bit is set in the Status Register. Once the LSD bit has been set, it cannot be reset until the PFMON voltage increases ~100 mV (typical) above the PMLO voltage. CS5461 7 ...
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... Symbol Min (DC, 50, 60 Hz) CMRR 80 (Gain = 10) IIN (Gain = 50) THD 80 All Gain Ranges -0.25 (50, 60 Hz) (Gain = 10) IC (Gain = 50) (Gain = 10) EII 30 (Gain = 50) 30 (Gain = 10 (Gain = 50) (Note 1) VOS (Note 1) FSE CS5461 = 25°C. A Min Typ Max Unit 3.3 5.25 V 4. -40 - +85 °C Typ Max Unit - ...
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... Notes: 3. The minimum FSCR is limited by the maximum allowed gain register value. DS546F2 (Continued) Symbol Min {(VIN+) - (VIN-)} VIN THD All Gain Ranges -0.25 All Gain Ranges IC (Note 2) EII N V (Note 1) VOS (Note 1) FSE -2.8 (Both Channels) OWR DCLK = MCLK/K (Note 3) FSCR -3 dB CS5461 Typ Max Unit 0 - 500 VA - 150 µ ± ...
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... Definition for PSRR: VREFIN tied to VREFOUT, VA 150 mV (zero-to-peak) (60 Hz) sinewave is imposed onto the + supply voltage at VA+ and VD+ pins. The “+” and “-” input pins of both input channels are shorted to VA-. Then the CS5461 is commanded to continuous conversion acquisition mode, and digital output data is collected for the channel under test ...
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... V out out Symbol V IH 0.6 VD+ XIN (VD+) - 0.5 SCLK and RESET 0.8 VD XIN SCLK and RESET (VD+) - 1.0 out out out CS5461 Min Typ Max Unit - - 0 1 0 ±1 ±10 µ ±10 µ ...
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... Pulse Width High t 10 Pulse Width Low computational flow diagram for the two data paths is shown in Fig. 2. The analog waveforms at CS5461 Min Typ Max Unit 2.5 4.096 20 MHz 1.0 µ 100 µs ...
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... Auto-Boot Sequence Timing (Not to Scale) Figure 1. CS5461 Read and Write Timing Diagrams DS546F2 SDI Write Timing (Not to Scale ...
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... Average Power Register. The average * ACoff - Σ Σ ÷ PulseRateF F out Energy - * P x off to - Pulse TBC * - Σ N Σ ÷ Avg + Energy - x out to - Pulse E dir * PulseRateE Σ Σ ÷ ACoff * DENOTES REGISTER NAME CS5461 V * RMS I * RMS DS546F2 ...
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... The signed output format is a two’s comple- ment format, and the output data words represent a normalized value between -1 and +1. signed data in the CS5461 output registers repre- sent normalized values between 0 and 1. A register value of 1 represents the maximum possible value. ...
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... This linearity is guaranteed for all four of ± the available full-scale input voltage ranges. Note that until the CS5461 is calibrated (see Cali- bration) the accuracy of the CS5461 (with respect to a reference line-voltage and line-current level on the power mains) is not guaranteed to within 0.1%. But the linearity of any given sample of ± ...
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... Therefore, for either channel, if the voltage level of a gain calibration input signal is low enough that it causes the CS5461 to attempt to set either gain reg- ister higher than 4, the gain calibration result will be invalid and all CS5461 results obtained while running A/D conversions will be invalid ...
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... If offset and gain calibration command bits are set, only the offset calibration will be performed. 4.4.6 Description of Calibration Algo- rithms The computational flow of the CS5461’s AC and DC gain/offset calibration sequences are illustrated in Figure 6. This figure applies to both the voltage channel and the current channel. ...
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... DC Gain Calibration Sequence Based on the level of the positive DC calibration voltage applied across the “+’ and “-” inputs, the CS5461 determines the DC Gain Register value by averaging the Instantaneous Register’s output sig- nal values over one computation cycle (N samples) and then dividing this average into 1. Therefore, af- ...
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... CS5461. Voltage and current transformers, as well as other sensor equipment applied to the front-end of the CS5461 inputs can often introduce a phase delay in the system, which distorts the phase relationship between the voltage and current signals being measured. The phase compensation bits PC[6:0] can be set to nullify this undesirable phase distortion between the two channels ...
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... On-Chip Temperature Sensor After a few minutes of normal-active operation in ‘continuous conversions’ data acquisition mode, the CS5461 will stabilize to a constant steady-state operating temperature. However, the CS5461’s op- erating temperature may be influenced by changes in the ambient temperature. Such ambient temper- ature fluctuations will cause some drift in the gain of the CS5461’ ...
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... INT pulse will be at least one DCLK cycle (DCLK = MCLK / K). 22 4.10 Voltage Sag-Detect Feature The CS5461 includes Status Register bit, VSAG; which indicates a sag in the power line voltage. In order for sag condition to be identified, the mea- sured V ...
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... A/D sampling period. A running total of the energy accumulation is maintained in an in- ternal register inside the CS5461 (not available to the user). After each A/D conversion cycle, the re- sult in the Power Register is multiplied by the value in the PulseRateE Register, and also by the value in ...
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... EDIR Figure 11. Mechanical Counter Format on EOUT and EDIR ative energy accumulation is reached in this regis- ter, the CS5461 will issue either a positive or negative energy pulse on the EOUT/EDIR pins. After the pulse or pulses are issued, a certain resid- ual amount of energy may be left over in this inter- nal energy accumulation register ...
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... V = 0.0006 V = 150 0.0075 Ω These sensor gain constants are used to calculate what the input voltage levels will be on the CS5461 inputs when the line-voltage and line-current are 220 V and 15 A. These values are V om 220 V = 132 mV ...
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... CS5461 drives CS low, provides a clock output on SCLK, and drives out-commands on SDO. It re- ceives the EEPROM data on SDI. The serial EE- PROM user-specified commands and register data that will be used by the CS5461 to change any of the default register values and begin conversions. 250mV 250mV ⋅ ...
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... National Semiconductor • Xicor These types of serial EEPROMs expect a specific 8-bit command word (00000011) in order to per- form a memory download. The CS5461 has been hardware programmed to transmit this 8-bit com- mand word to the EEPROM at the beginning of the auto-boot sequence. CS5461 initialization ...
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... SERIAL PORT OVERVIEW The CS5461's serial port incorporates a state ma- chine with transmit/receive buffers. The state ma- chine interprets 8 bit command words on the rising edge of SCLK. Upon decoding of the command word, the state machine performs the requested command or prepares for a data transfer of the ad- dressed register ...
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... In the sleep state, all circuitry except the digital clock generator and the instruction decoder is turned off. Bringing the CS5461 out of sleep state requires more time than out of stand-by state, because of the extra time needed to re-start and re-stabilize the analog clock signal. ...
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... Temperature Register Reserved † Pulse width register for mechanical counter output mode Reserved † Voltage Sag Level Threshold Register. Level Voltage Sag Duration Register. Duration Reserved † Mask Register Reserved † Control Register Reserved † Reserved † Reserved † CS5461 th SCLK. DS546F2 ...
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... MCLK received after detecting a reset event. The in- ternal register values are also set to their default val- ues after initial power-on of the device. The CS5461 will then assume its active state. 6.5 Serial Port Initialization It is possible for the serial interface to become un- synchronized, with respect to the SCLK input ...
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... To insure that the CS5461 is oper- ating in the active state; perform one of the three actions below: 1) Power on the CS5461. (Or if the device is al- ready powered on, recycle the power.) 2) Software Reset 3) Hardware Reset If the device is in sleep state or in stand-by state, is- suing the Power-Up/Halt command will also insure that the device is in active state ...
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... Control the use of the High Pass Filter on the voltage Channel High-pass filter disabled (default High-pass filter enabled IHPF Control the use of the High Pass Filter on the Current Channel. DS546F2 PC4 PC3 PC2 IMODE IINV iCPU K3 CS5461 Igain PC1 PC0 EPP EOP EDP ...
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... The Cycle Count Register value (denoted as ‘N’) determines the length of one energy and RMS computation cycle. During continuous conversions, the computation cycle frequency is (MCLK/K)/(1024∗N -17 ..... -16 ..... ..... CS5461 -18 -19 -20 -21 - -17 -18 -19 -20 - ...
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... V . The results are in the range of RMS RMS - -17 ..... CS5461 -18 -19 -20 -21 - The results will be within in the AVG -19 -20 -21 -22 - ...
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... Current Out of Range. Set when the magnitude of the calibrated current value is too large or too small to fit in the Instantaneous Current Register -17 ..... CRDY EOOR VOD IOD CS5461 -18 -19 -20 -21 - IOR VOR LSD VSAG IC DS546F2 LSB ...
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... This sequence lasts ~(6N + 30) A/D conversion cycles (where N is the value of the Cycle-Count Register). DRDY will be asserted at the end of the calibration. The register value may be read and stored for future system offset compensation. DS546F2 Registers, have been met -18 ..... CS5461 level -19 -20 -21 -22 - LSB -24 ...
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... RMS CS5461 -11 -12 -13 -14 - -18 ...
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... CPUCLK external drive pin. NOOSC 1 = saves power by disabling the crystal oscillator circuit. STEP 1 = enables stepper-motor signals on the EOUT/EDIR pins. DS546F2 ..... INTOD CS5461 FAC EAC STOP NOCPU NOOSC ...
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... In this type of shunt-resistor configuration, the common-mode level of the CS5461 must be referenced to the hot side of the power line; which means the com- mon-mode potential of the CS5461 will typically oscillate to very high voltage levels with respect to earth ground potential ...
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... VA+ VD+ CS5461 17 PFMON 9 VIN+ 2 CPUCLK 1 2.5 MHz to XOUT 20 MHz Optional 10 24 VIN- XIN Clock 16 Source IIN+ 19 RESET Idiff Serial SDO 15 Data 5 IIN- SCLK Interface 20 INT 12 VREFIN 22 11 VREFOUT EDIR 21 EOUT VA- DGND 13 4 Mech. Counter or Stepper Motor CS5461 41 ...
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... V- 10 VIN- 16 IIN Ω Burden 1k Ω 15 IIN VREFIN 11 VREFOUT 0.1 µF To Service CS5461 5 kΩ 10 kΩ 10 Ω 0.1 µ VD+ CS5461 17 PFMON 2 CPUCLK 1 2.5 MHz to XOUT 20 MHz Optional 24 XIN Clock Source 19 RESET 7 CS Serial 23 SDI Data 6 SDO Interface 5 SCLK 20 INT ...
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... PLANE SIDE VIEW NOM MAX MIN -- 0.084 -- 0.006 0.010 0.05 0.068 0.074 1.62 -- 0.015 0.22 0.323 0.335 7.90 0.307 0.323 7.40 0.209 0.220 5.00 0.026 0.030 0.55 0.03 0.041 0.63 4° 8° 0° JEDEC #: MO-150 Controlling Dimension is Millimeters. CS5461 1 E1 ∝ END VIEW L MILLIMETERS NOM MAX -- 2.13 0.13 0.25 1.73 1.88 -- 0.38 8.20 8.50 7.80 8.20 5.30 5.60 0.65 0.75 0.75 1.03 4° 8° NOTE 2 ...
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... Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. 44 Changes www.cirrus.com CS5461 DS546F2 ...
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... DS546F2 CS5461 45 ...