pcf8548 NXP Semiconductors, pcf8548 Datasheet - Page 6

• Manufacturer Part Number: pcf8548
• Description: 65 X 102 Pixels Matrix Lcd Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
8
8.1
The on-chip oscillator provides the clock signal for the
display system. No external components are required and
the OSC input must be connected to V
clock signal (if used), is connected to this input.
8.2
The I
commands sent via the I
and sends it to the RAM.
8.3
The display control logic generates the control signals to
read from the RAM via the 102 bits parallel port. It also
generates the control signals for the row and column
drivers.
8.4
The PCF8548 contains a 65
stores the display data. The RAM is divided into 8 banks of
102 bytes and 1 bank of 102 bits [(8
During RAM access, data is transferred to the RAM via the
I
between the X address and column output number.
1999 Aug 16
2
C-bus interface. There is a direct correspondence
65
BLOCK DIAGRAM FUNCTIONS
2
C-bus interface receives and executes the
Oscillator
I
Display control logic
Display Data RAM (DDRAM)
2
C-bus interface
102 pixels matrix LCD driver
2
C-bus. It also receives RAM data
102 bit static RAM which
8 + 1)
DD1
. An external
102 bits].
6
8.5
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not disturbed by operations on the I
8.6
The PCF8548 contains 65 row and 102 column drivers,
which connect the appropriate LCD bias voltages to the
display in accordance with the data to be displayed.
Figure 2 shows typical waveforms. Unused outputs should
be left unconnected.
9
Immediately following Power-on, all internal registers and
the RAM content are undefined. A reset pulse must first be
applied.
Reset is accomplished by applying an external RES pulse
(active LOW). When reset occurs within the specified time
all internal registers are initialized, however the RAM is still
undefined. The state after reset is described in
Section 12.1.
The RES input must be 0.3 V
V
goes HIGH (see Fig.17).
DD(min)
INITIALIZATION
Timing generator
LCD row and column drivers
(or higher) within a maximum time t
DD
when V
Product specification
PCF8548
DD
VHRL
reaches
2
after V
C-bus.
DD