pcf8548 NXP Semiconductors, pcf8548 Datasheet - Page 5

• Manufacturer Part Number: pcf8548
• Description: 65 X 102 Pixels Matrix Lcd Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7
7.1
These pads output the row signals.
7.2
These pads output the column signals.
7.3
V
V
7.4
V
voltage generator. Both have to be at the same voltage
and must be connected together outside of the chip. If the
internal voltage generator is not used, they should both be
connected to power or to the V
V
This voltage can be a different voltage than V
V
7.5
Internally generated positive power supply for the liquid
crystal display. An external LCD supply voltage can be
supplied using the V
to be connected to ground, and the internal voltage
generator has to be programmed to zero. If the PCF8548
is in power-down mode, the external LCD supply voltage
must be switched off.
7.6
Positive power supply for the liquid crystal display. If the
internal voltage generator is used, the two supply rails
V
external capacitor must be connected (see Fig.19).
7.7
V
multiplier regulation.
If the internal voltage generator is used then V
must be connected to V
voltage is used then V
ground.
1999 Aug 16
SS2
DD1
DD2
DD1
DD3
LCDIN
LCDSENSE
65
PIN FUNCTIONS
.
.
is related to V
and V
is used as the power supply for the rest of the chip.
R0 to R64: row driver outputs
C0 to C101: column driver outputs
V
V
V
V
V
(V
and V
SS1
DD1
LCDIN
LCDOUT
LCDSENSE
LCD
102 pixels matrix LCD driver
is the input voltage for the internal voltage
DD3
and V
to V
)
LCDOUT
: LCD power supply
are the supply voltages for the internal
: LCD power supply
DD3
: voltage multiplier regulation input
SS2
DD2
: positive power supply rails
LCDIN
must be connected together and an
: negative power supply rails
LCDSENSE
and V
LCDOUT
pad. In this case, V
DD3
. If an external supply
DD1
must be connected to
and V
pad.
SS1
is related to
DD2
LCDOUT
LCDSENSE
and
has
5
7.8
T1 and T3 to T7 must be connected to V
connected to V
open-circuit; not accessible to user.
7.9
Serial data and acknowledge lines for the I
By connecting SDAIN to SDAOUT, the SDA line becomes
fully I
(SDAOUT) separated from the serial data line is
advantageous in Chip-On-Glass (COG) applications.
In COG applications where the track resistance from the
SDAOUT pad to the system SDA line can be significant, a
potential divider is generated by the bus pull-up resistor
and the Indium Tin Oxide (ITO) track resistance. It is
possible that during the acknowledge cycle the PCF8548
will not be able to create a valid logic 0 level. By splitting
the SDA input from the output the device could be used in
a mode that ignores the acknowledge bit. In COG
applications where the acknowledge cycle is required, it is
necessary to minimize the track resistance from the
SDACK pad to the system SDA line to guarantee a valid
LOW level.
7.10
I
7.11
Two different slave addresses can be selected using the
SA0 pad. This allows two PCF8548 LCD drivers to be
connected to the same I
7.12
When the on-chip oscillator is used this input must be
connected to V
connected to this input.
7.13
This signal is used to reset the device. The signal is active
LOW.
2
C-bus serial clock signal input.
2
C-bus compatible. Having the acknowledge output
T1 to T12: test pads
SDAIN and SDAOUT: I
SCL: I
SA0: slave address
OSC: oscillator
RES: reset
2
C-bus clock signal
DD1
DD1
. T2 and T9 to T12 must be left
. An external clock signal, if used, is
2
C-bus.
2
C-bus data lines
Product specification
SS1
PCF8548
2
C-bus.
. T8 must be