pcf8548 NXP Semiconductors, pcf8548 Datasheet - Page 15

• Manufacturer Part Number: pcf8548
• Description: 65 X 102 Pixels Matrix Lcd Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
11.2
The PCF8548 supports command, data write and status
read access.
Before any data is transmitted on the I
which should respond is addressed first. Two 7-bit slave
addresses (0111100 and 0111101) are reserved for the
PCF8548. The least significant bit of the slave address is
set by connecting the input SA0 to either logic 0 (V
logic 1 (V
The I
The sequence is initiated with a START condition (S) from
the I
All slaves with the corresponding address acknowledge in
parallel, all the others will ignore the I
acknowledgement, one or more command words follow
which define the status of the addressed slaves.
A command word consists of a control byte, which defines
Co and D/C, plus a data byte (see Fig.14 and Table 1).
The last control byte is tagged with a cleared most
significant bit (i.e. the continuation bit Co). After a control
byte with a cleared Co bit, only data bytes will follow. The
state of the D/C bit defines whether the data byte is
interpreted as a command or as RAM data.
1999 Aug 16
handbook, full pagewidth
65
2
2
C-bus master which is followed by the slave address.
C-bus protocol is illustrated in Fig.14.
I
2
Write mode
Read mode
S 0 1 1 1 1 0
S 0 1 1 1 1 0
C-bus protocol
DD1
102 pixels matrix LCD driver
slave address
slave address
).
acknowledgement
acknowledgement
from PCF8548
from PCF8548
S
A
S
A
0
0
0 A
1 A
Co
1
DC
status bytes
2
control byte
C-bus transfer. After
2
C-bus, the device
acknowledgement
acknowledgement
from PCF8548
command word
from master
2n
Fig.14 I
A
A
0 bytes
P
SS1
) or
data byte
2
C-bus protocol.
15
The control and data bytes are also acknowledged by all
addressed slaves on the bus.
After the last control byte, depending on the D/C bit setting,
either a series of display data bytes or command data
bytes may follow. If the D/C bit is set to logic 1, these
display bytes are stored in the display RAM at the address
specified by the data pointer. The data pointer is
automatically updated and the data is directed to the
intended PCF8548 device. If the D/C bit of the last control
byte is set to logic 0, these command bytes will be
decoded and the setting of the device will be changed
according to the received commands. The
acknowledgement after each byte is made only by the
addressed slave. At the end of the transmission the
I
If the R/W bit is set to logic 1 the chip will output data
immediately after the slave address if the D/C bit, which
was sent during the last write access, is set to logic 0. If no
acknowledge is generated by the master after a byte, the
driver stops transferring data to the master.
acknowledgement
2
C-bus master issues a STOP condition (P).
from PCF8548
A
Co
0
DC
control byte
1 byte
acknowledgement
Co
0 1
from PCF8548
slave address
DC
PCF8548
control byte
1 1
0 0 0 0 0 0
A
MSB . . . . . . . . . . . LSB
1 0
data byte
n
S
A
0
R/
W
Product specification
0 bytes
A
acknowledgement
PCF8548
from PCF8548
MGS401
A P