pcf8548 NXP Semiconductors, pcf8548 Datasheet - Page 18

• Manufacturer Part Number: pcf8548
• Description: 65 X 102 Pixels Matrix Lcd Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
12.2
12.2.1
12.2.2
When V = 0, the horizontal addressing is selected.
The data is written to the RAM as shown in Fig.4. When
V = 1, the vertical addressing is selected. The data is
written to the RAM as shown in Fig.5.
12.2.3
When H = 0 the commands ‘display control’, ‘set HV-gen
stages’, ‘set Y address’ and ‘set X address’ can be
performed. When H = 1 the other commands can be
executed. The commands ‘write data’ and ‘function set’
can be executed in both cases.
12.2.4
When MX = 0, the display RAM is written from left to right
(X = 0 is on the left side of the display, X = 100 is on the
right side of the display). When MX = 1 the display RAM is
written from right to left (X = 0 is on the right side of the
display, X = 100 is on the left side of the display).
Thus, if a horizontally mirroring of the display is desired the
RAM must first be rewritten.
Table 3 X and Y address ranges
Note
1. In bank 8 only the MSB is accessed.
1999 Aug 16
All LCD outputs at V
Bias generator and V
Oscillator off (external clock possible)
V
RAM contents not cleared (RAM data can be written)
V
65
LCD
LCD
Y
0
0
0
0
0
0
0
0
1
Function set
3
can be disconnected
output is discharged to V
P
V
H
MX
102 pixels matrix LCD driver
OWER
-D
OWN
Y
0
0
0
0
1
1
1
1
0
2
SS
(PD)
LCD
(display off)
generator off
SS
Y
0
0
1
1
0
0
1
1
0
.
1
Y
0
1
0
1
0
1
0
1
0
0
18
bank 8 (display RAM); note 1
12.2.5
When MY = 1, the display is mirrored vertically.
A change of this bit has an immediate effect on the display.
12.3
12.3.1
The bits D and E select the display mode (see Table 2).
12.4
12.4.1
Bit TRS enables the top row pad blocks to be mirrored.
This is used to enable flexibility in the wiring of the row
lines from the PCF8548 to the LCD cell (e.g. COG or TCP
wiring). When TRS = 0 rows 19 to 32 and rows 51 to 64
are organized as illustrated in Fig.22. When TRS = 1 rows
19 to 32 and rows 51 to 64 are mirrored and organized as
illustrated in Fig.23.
12.4.2
Bit BRS enables the bottom row pad blocks to be mirrored.
This is used to enable flexibility in the wiring of the row
lines from the PCF8548 to the LCD cell (e.g. COG or TCP
wiring). When BRS = 0 rows 0 to 18 and rows 33 to 50 are
organized as illustrated in Fig.22. When BRS = 1 rows
0 to 18 and rows 33 to 50 are mirrored and organized as
illustrated in Fig.23.
12.5
Y[3 : 0] defines the Y address vector address of the RAM.
bank 0 (display RAM)
bank 1 (display RAM)
bank 2 (display RAM)
bank 3 (display RAM)
bank 4 (display RAM)
bank 5 (display RAM)
bank 6 (display RAM)
bank 7 (display RAM)
Display control
Display configuration
Set Y address of RAM
CONTENT
MY
D
TRS
BRS
AND
E
ALLOWED X RANGE
Product specification
PCF8548
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101