s908ey8ad4cfjer Freescale Semiconductor, Inc, s908ey8ad4cfjer Datasheet - Page 233

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s908ey8ad4cfjer

Manufacturer Part Number
s908ey8ad4cfjer
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Enter monitor mode with pin configuration shown in
rising edge of RST latches monitor mode. Once monitor mode is latched, the levels on the port pins
except PTA0 can change.
Once out of reset, the MCU waits for the host to send eight security bytes (see
security bytes, the MCU sends a break signal (10 consecutive 0s) to the host, indicating that it is ready to
receive a command.
19.3.1.1 Normal Monitor Mode
If V
When monitor mode was entered with V
as long as V
This condition states that as long as V
V
then the COP will be disabled. In the latter situation, after V
removed from the IRQ pin in the interest of freeing the IRQ for normal functionality in monitor mode.
Freescale Semiconductor
TST
2
3
5
TST
1 µF
1 µF
DB9
is applied to RST after the initial reset to get into monitor mode (when V
is applied to IRQ upon monitor mode entry, the bus frequency is a divide-by-four of the input clock.
+
+
7
8
1
3
4
5
TST
C1+
C1–
C2+
C2–
is applied to either IRQ or RST.
MAX232
GND
V
V+
V–
CC
Figure 19-11. Forced Monitor Mode (IRQ = V
16
15
2
10
6
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
9
V
DD
+
+
1 µF
1 µF
2
74HC125
TST
1
+
TST
3
1 µF
is maintained on the IRQ pin after entering monitor mode, or if
74HC125
on IRQ, the computer operating properly (COP) is disabled
6
4
5
Table 19-1
V
DD
10 kΩ
TST
* Value not critical
is applied to the RST pin, V
by pulling RST low and then high. The
10 k*
N.C.
N.C.
RST
OSC1
IRQ
PTA0
SS
)
MC68HC908EY16
TST
19.3.2
was applied to IRQ),
Monitor Module (MON)
Security). After the
PTB4
PTB3
PTA1
V
V
V
V
DDA
SSA
DD
SS
TST
10 k
can be
V
DD
N.C.
N.C.
0.1 µF
233

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