s908ey8ad4cfjer Freescale Semiconductor, Inc, s908ey8ad4cfjer Datasheet - Page 186

• Manufacturer Part Number: s908ey8ad4cfjer
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Serial Peripheral Interface (SPI) Module
SPE — SPI Enable Bit
SPTIE — SPI Transmit Interrupt Enable Bit
15.13.2 SPI Status and Control Register
The SPI status and control register contains flags to signal the following conditions:
The SPI status and control register also contains bits that perform these functions:
SPRF — SPI Receiver Full Bit
ERRIE — Error Interrupt Enable Bit
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This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI (see
Resetting the
This read/write bit enables CPU interrupt requests generated by the SPTE bit. SPTE is set when a byte
transfers from the transmit data register to the shift register. Reset clears the SPTIE bit.
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This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data
register. SPRF generates a CPU interrupt request if the SPRIE bit in the SPI control register is set also.
During an SPRF CPU interrupt, the CPU clears SPRF by reading the SPI status and control register
with SPRF set and then reading the SPI data register. Any read of the SPI data register clears the
SPRF bit.
Reset clears the SPRF bit.
This read-only bit enables the MODF and OVRF flags to generate CPU interrupt requests. Reset
clears the ERRIE bit.
1 = SPI module enabled
0 = SPI module disabled
1 = SPTE CPU interrupt requests enabled
0 = SPTE CPU interrupt requests disabled
1 = Receive data register full
0 = Receive data register not full
1 = MODF and OVRF can generate CPU interrupt requests
0 = MODF and OVRF cannot generate CPU interrupt requests
Receive data register full
Failure to clear SPRF bit before next byte is received (overflow error)
Inconsistent logic level on SS pin (mode fault error)
Transmit data register empty
Enable error interrupts
Enable mode fault error detection
Select master SPI baud rate
Address:
Reset:
Read:
Write:
SPI). Reset clears the SPE bit.
Figure 15-13. SPI Status and Control Register (SPSCR)
$000E
SPRF
Bit 7
0
MC68HC908EY16 • MC68HC908EY8 Data Sheet, Rev. 10
= Unimplemented
ERRIE
6
0
OVRF
5
0
MODF
4
0
SPTE
3
1
MODFEN
2
0
SPR1
1
0
Freescale Semiconductor
SPR0
Bit 0
0
15.9