sg2567fbd28452ibdc ETC-unknow, sg2567fbd28452ibdc Datasheet - Page 8

• Manufacturer Part Number: sg2567fbd28452ibdc
• Description: Dram Module Ddr2 Sdram 2gbyte 240fbdimm
• Manufacturer: ETC-unknow

AMB Pin Description
FBD Channel Signals (Signal Count: 99)
DDR2 Interface Signals (Signal Count: 175)
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Pin Name
SCK
SCK#
PN0 ~ PN13
PN0# ~ PN13#
PS0 ~ PS9
PS0# ~ PS9#
SN0 ~ SN13
SN0# ~ SN13#
SS0 ~ SS9
SS0# ~ SS9#
FBDRES
Pin Name
DQS0 ~ DQS8
DQS0# ~ DQS8#
DQS9 ~ DQS17/
DM0 ~ DM8
DQS9# ~ DQS17#
DQ0 ~ DQ63
CB0 ~ CB7
A0A ~ A15A,
A0B ~ A15B
BA0A ~ BA2A,
BA0B ~ BA2B
RASA#, RASB#,
CASA#, CASB#,
WEA#, WEB#
ODTA, ODTB
CKE0A, CKE1A,
CKE0B, CKE1B
CS0A#, CS1A#,
CS0B#, CS1B#
CLK0 ~ CLK3
CLK0# ~ CLK3#
Pin Description
Positive line of the differential pair of system clock inputs.
Primary Northbound Data, positive lines.
Primary Northbound Data, negative lines.
Secondary Northbound Data, positive lines.
Secondary Northbound Data, negative lines.
To an external precision calibration resistor connected to V
Pin Description
Data Strobes, negative lines.
Data Strobes (x4 DRAM only), positive lines. These signals are driven low to x8
DRAM on writes.
Data Strobes (x4 DRAM only), negative lines.
Data.
Checkbits.
Address.
Bank Select Addresses.
Command Signals.
On-Die Termination Enable.
Clock Enable (One per Rank).
Chip Select (One per Rank).
CLK[1:0] used on 9 and 18 device DIMMs, CLK[3:0] used on 36 device DIMMs.
CLK[3:2] should be output disabled when not in use.
Clock, Negative lines.
Negative line of the differential pair of system clock inputs.
Primary Southbound Data, positive lines.
Primary Southbound Data, negative lines.
Secondary Southbound Data, positive lines.
Secondary Southbound Data, negative lines.
Data Strobes, positive lines.
SG2567FBD28452UUDC
CC
.
August 29, 2007
1
1
14
14
10
10
14
14
10
1
9
9
9
64
8
32
6
6
2
4
4
4
4
Count
10
Count
9
8