sg2567fbd28452ibdc ETC-unknow, sg2567fbd28452ibdc Datasheet - Page 22

• Manufacturer Part Number: sg2567fbd28452ibdc
• Description: Dram Module Ddr2 Sdram 2gbyte 240fbdimm
• Manufacturer: ETC-unknow

DDR2 I
Notes:
1.
2.
3.
Corporate Headquarters: P. O. Box 1757, Fremont, CA 94538, USA • Tel:[phone] • Fax:[phone] • E-mail: [e-mail]
Europe: 5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: [phone] • Fax: [phone]
Asia/Pacific: Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: [phone] • Fax: [phone]
I
I
I
I
I
I
CC_TRAINING
DD_TRAINING
CC_ACTIVE_1
DD_ACTIVE_1
CC_ACTIVE_2
DD_ACTIVE_2
I
I
I
I
I
I
CC_IDLE_0
DD_IDLE_0
CC_IDLE_1
DD_IDLE_1
CC_IDLE_2
DD_IDLE_2
Total Power = I
V
FBDIMM Power was calculated on the basis of DRAM and AMB Values in the datasheet.
Symbol
I
I
CC_L0s
DD_L0s
CC(max)
DD
Specifications and Conditions
= 1.545V; V
CC
Parameter/Condition
Idle current, single or last FBDIMM: L0 state, idle (0 BW);
primary channel enabled, secondary channel disabled, CKE
high; command and address lines stable, DDR2 SDRAM clock
active.
Total Power
Idle current, first FBDIMM: L0 state, idle (0 BW); primary and
secondary channels enabled, CKE high; command and
address lines stable, DDR2 SDRAM clock active.
Total Power
Idle current, DDR2 SDRAM power down: L0 state, idle
(0 BW); primary and secondary channels enabled, CKE low;
command and address lines floated, DDR2 SDRAM clock
active; ODT and CKE driven LOW.
Total Power
Active Power: L0 state; 50% DDR2 SDRAM BW, 67% READ,
33% WRITE; primary and secondary channels enabled, CKE
high; DDR2 SDRAM clock active.
Total Power
Active Power, data pass through: L0 state; 50% DDR2
SDRAM BW to downstream FBDIMM, 67% READ, 33%
WRITE; primary and secondary channels enabled; command
and address lines stable, CKE high; DDR2 SDRAM clock
active.
Total Power
Channel standby: Average power over 42 frames where the
channel enters and exits L0s; DDR2 SDRAM devices idle
(0 BW); CKE low; command and address lines floated; DDR2
SDRAM clock active, ODT and CKE driven LOW.
Total Power
Training: Primary and secondary channels enabled; 100%
toggle on all channel lanes; DDR2 SDRAM devices idle (0
BW); CKE high, command and address lines stable; DDR2
SDRAM clock active.
Total Power
x V
CC(max)
DD(max)
+ I
= 1.9V.
DD
x V
DD(max)
.
SG2567FBD28452UUDC
Supply
Power
1.5V
1.8V
1.5V
1.8V
1.5V
1.8V
1.5V
1.8V
1.5V
1.8V
1.5V
1.8V
1.5V
1.8V
August 29, 2007
DDR2-
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
667
Units
W
W
W
W
W
W
W
A
A
A
A
A
A
A
A
A
A
A
A
A
A
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