sg2567fbd28452ibdc ETC-unknow, sg2567fbd28452ibdc Datasheet - Page 3

• Manufacturer Part Number: sg2567fbd28452ibdc
• Description: Dram Module Ddr2 Sdram 2gbyte 240fbdimm
• Manufacturer: ETC-unknow

Features:
• High-Speed differential PTP link between Controller & AMB
• SMBus Interface access to AMB Configuration Registers
FBD/AMB Specifications:
Fully Buffered DIMM (FBD) provides a high memory bandwidth, large capacity channel solution that has a narrow
host interface. Fully Buffered DIMMs use commodity DRAMs isolated from the channel behind a buffer (AMB) on
the DIMM. The memory capacity is 288 devices per channel and total memory capacity scales with DRAM bit den-
sity. Currently, FBD/AMB specification is broken-out into the following specifications:
1. FBD Design Specification: This specification defines the electrical and mechanical requirements for 240-pin,
2. FBD Architecture and Protocol Specification: This specification covers Overview, Channel Initialization, Chan-
3. FBD AMB Specification: The Advanced Memory Buffer allows buffering of memory traffic to support large
4. FBD High-Speed Differential PTP Link Specification: This specification defines the high-speed differential
5. FBD SPD Specification: This specification describes the Serial Presence Detect (SPD) values for FBD.
6. FBD DFx Specification: The FB-DIMM DFx spec covers Design for Test (DFT), Design for Manufacturing
Corporate Headquarters: P. O. Box 1757, Fremont, CA 94538, USA • Tel:[phone] • Fax:[phone] • E-mail: [e-mail]
Europe: 5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: [phone] • Fax: [phone]
Asia/Pacific: Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: [phone] • Fax: [phone]
Device Speed
DDR2-667
PC2-4200/PC2-5300/PC2-6400, 72 bit-wide, Fully Buffered Double Data Rate Synchronous DRAM Dual In-
Line Memory Modules (DDR2 SDRAM FBDs).
nel Protocol, and Reliability, Availability, and Serviceability (RAS) features of FBDIMM architecture.
memory capacities. This specification covers information about various AMB interfaces (Channel/DRAM), Test
& Initialization functions, SMBus Interface, Clocking, Registers, etc.
point-to-point signaling link for FB-DIMM, operating at the buffer supply voltage of 1.5V that is provided at the
FBDIMM connector. This specification also applies to FBD host chips which may operate with a different sup-
ply voltage. The link consists of a transmitter and a receiver and the interconnect in between them. The trans-
mitter sends serialized bits into a lane and the receiver accepts the electrical signals of the serialized bits and
transforms them into a serialized bit-stream.The link utilizes a derived clock approach and transmitter de-
emphasis to compensate for channel loss characteristics.
(DFM) and Design for Validation (DFV) requirements and implementation guidelines for Fully Buffered DIMM
technology.
2GByte (256Mx72) DDR2 SDRAM Module - 128Mx4 Based
CL (Device)
3.0/4.0/5.0
Cycle Time
3.0ns
240-pin Fully Buffered DIMM, ECC
Link Speed
4.0Gb/s
• AMB allows up to 8 Double-Rank DIMMs/Channel (288
• MEMBIST and IBIST Test Functions
• V
• V
• V
• V
• Single Rank Module (JEDEC Raw Card “E”)
• Lead Finish : Gold
devices) Transparent Mode for DRAM Test
DD
CC
TT
DDSPD
= 0.9V +/- 0.036V (DRAM Interface Termination)
= V
= 1.5V +/- 0.045V (for AMB)
SG2567FBD28452UUDC
DDQ
= 3.3V +/- 0.3V
= 1.8V +/- 0.1V (for DDR2 SDRAM)
August 29, 2007
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