sg2567fbd28452ibdc ETC-unknow, sg2567fbd28452ibdc Datasheet - Page 5

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sg2567fbd28452ibdc

Manufacturer Part Number
sg2567fbd28452ibdc
Description
Dram Module Ddr2 Sdram 2gbyte 240fbdimm
Manufacturer
ETC-unknow
Datasheet
Pin Description:
DIMM Connector Pin Description
Corporate Headquarters: P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe: 5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific: Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
Symbol
SCK
SCK#
PN0 ~ PN13
PN0# ~ PN13#
PS0 ~ PS9
PS0# ~ PS9#
SN0 ~ SN13
SN0# ~ SN13#
SS0 ~ SS9
SS0# ~ SS9#
SCL
SDA
SA0 ~ SA2
VID0 ~ VID1
V
V
V
V
V
RESET#
RFU
DNU/M_Test
CC
DD
SS
TT
DDSPD
Note: System Clock Signals (SCK & SCK#) switch at one-half the DRAM CK/CK# frequency.
Type
Input
Input
Output
Output
Input
Input
Input
Output
Input/Output
Input/Output
Supply
Supply
Supply
Supply
Supply
Supply
Input
-
Input
Output
Input
-
Polarity
Positive Edge
Negative Edge
Positive Edge
Negative Edge
Negative Edge
Positive Edge
Negative Edge
-
-
-
-
-
-
-
-
Active Low
-
Positive Edge
Positive Edge
Negative Edge
-
-
Function
Positive line of the differential pair of system clock inputs.
Negative line of the differential pair of system clock inputs.
Primary Northbound Data, positive lines.
Primary Northbound Data, negative lines.
Primary Southbound Data, positive lines.
Primary Southbound Data, negative lines.
Secondary Northbound Data, positive lines.
Secondary Northbound Data, negative lines.
Secondary Southbound Data, positive lines.
Secondary Southbound Data, negative lines.
Serial Presence Detect (SPD) for Clock Input.
SPD Data Input/Output.
SPD Address Inputs, also used to select the DIMM number in the AMB.
Voltage ID: These pins must be unconnected for DDR2-based Fully
Buffered DIMMs.
VID0 is V
VID1 is V
AMB Core Power and AMB Channel Interface Power(1.5 Volt).
DRAM Power and AMB DRAM I/O Power(1.8 Volt).
Ground.
DRAM Address/Command/Clock termination Power (V
SPD Power (3.3 Volt).
Advanced Memory Buffer (AMB) reset signal.
Reserved for Future Use.
The DNU/M_Test pin provides an external connection for testing the
margin of V
is not intended to be used in normal system operation and must not
be connected (DNU) in a system.
DD
CC
REF
value: OPEN = 1.8V, GND = 1.5V;
value: OPEN = 1.5V, GND = 1.2V;
which is produced by a voltage divider on the module. It
SG2567FBD28452UUDC
August 29, 2007
DD
/2).
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