sg2567fbd28451ibdc ETC-unknow, sg2567fbd28451ibdc Datasheet - Page 30

• Manufacturer Part Number: sg2567fbd28451ibdc
• Description: Dram Module Ddr2 Sdram 2gbyte 240fbdimm
• Manufacturer: ETC-unknow

Notes:
1. Specified at the package pins into a timing and voltage compliant test setup. Note that the signal levels at the
2. Single-ended voltages below that value that are simultaneously detected on D+ and D- are interpreted as the
3. Multiple lanes need to detect the EI condition before the device can act upon the EI detection.
4. Specified at the package pins into a timing and voltage compliant test setup.
5. The single-pulse mask provides sufficient symbol energy for reliable RX reception. Each symbol must comply
6. The relative amplitude ratio limit between adjacent symbols prevents excessive intersymbol interference in the
7. This number does not include the effects of the SSC or reference clock jitter.
8. This number includes setup and hold of the RX sampling flop.
9. Defined as the dual-dirac deterministic timing error.
10. Allows for 15mV DC offset between transmit and receive devices.
11. The received differential signal must satisfy both this ratio as well as the absolute maximum AC peak-to-peak
12. One of the components that contribute to the deterioration of the return loss is the ESD structure which needs
13. The termination small signal resistance tolerance across voltages from 100mV to 400mV shall not exceed +/-
14. This number represents the lane-to-lane skew between TX and RX pins and does not include the transmitter
15. Mesured from the reference clock edge to the center of the input eye. This specification must be met across
16. This bandwidth number assumes the specified minimum data transition density. Maximum jitter at 0.2 MHz is
17. The specified time includes the time required to forward the EI entry condition.
18. BER per differential lane.
V
V
V
R
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RX-DIFFp-p
RX-CM
RX-CM-AC
RX-MATCH-DC
pad will be lower than that at the pin.
Electrical Idle condition. Worst case margins are determined for the case with transmitter using small voltage
swing.
with both the single-pulse mask and the cumulative eyemask.
RX. Each symbol must comply with the peak amplitude ratio with regard to both the preceding and subsequent
symbols.
common mode specification. For example, if V
mode is lesser of (200mV *0.45 = 90mV) and V
to be carefully designed.
5W with regard to the average of the values measured at 100mV and 400mV for that pin.
output skew from the component driving the signal to the receiver. This is one component of the end-to-end
channel skew in the AMD specification.
specified voltage and temperature ranges for a single component. Drift rate of the change is signicantly below
the tracking capability of the receiver.
0.05 UI.
= DC
= ((Max
= 2 x
(avg)
= 2 x ((
⏐
of (
⏐
V
V
RX-D+
⏐
RX-D+
⏐
V
R
RX-D+
RX-D+
- V
+ V
RX-D-
+ V
RX-D-
- R
RX-D-
RX-D-
⏐
(EQ5)
⏐
)/2) - ((Min
⏐
⏐
/2) (EQ6)
) / (
⏐
R
RX_DIFFp-p
RX-D+
⏐
RX-CM-AC-p-p
V
RX-D+
+ R
RX-D-
+ V
is 200mV, the maximum AC peak-to-peak common
RX-D-
.
⏐
SG2567FBD28451UUDC
)) (EQ8)
⏐
)/2) (EQ7)
January 15, 2008
30