sg2567fbd28451ibdc ETC-unknow, sg2567fbd28451ibdc Datasheet
sg2567fbd28451ibdc
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sg2567fbd28451ibdc Summary of contents
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... Part Numbers Description SG2567FBD28451IBDC 256Mx72 (2GB), DDR2, 240-pin Fully Buffered DIMM, ECC, 128Mx4 Based, PC2-6400, DDR2-800-555, 30.35mm, Green Module (RoHS Compliant). Label: 2GB 2Rx4 PC2-6400F-555-11-E_* SG2567FBD28451SEDC 256Mx72 (2GB), DDR2, 240-pin Fully Buffered DIMM, ECC, 128Mx4 Based, PC2-6400, DDR2-800-555, 30.35mm, Green Module (RoHS Compliant). ...
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January 15, 2008 Datasheet released. Corporate Headquarters Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com Europe: 5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: ...
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DDR2 SDRAM Module - 128Mx4 Based 240-pin Fully Buffered DIMM, ECC Features: Device Speed CL (Device) Cycle Time Link Speed DDR2-800 3.0/4.0/5.0 2.5ns • High-Speed differential PTP link between Controller & AMB • SMBus Interface access to AMB ...
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DDR2 240-Pin FB-DIMM Pin List Pin Pin Pin Pin Pin No. Name No. Name No PN3 PN3 PN4 64 SS ...
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Pin Description: DIMM Connector Pin Description Symbol Type Polarity SCK Input Positive Edge SCK# Input Negative Edge PN0 ~ PN13 Output Positive Edge PN0# ~ PN13# Output Negative Edge PS0 ~ PS9 Input Positive Edge PS0# ~ PS9# Input Negative ...
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FBD System Block Diagram N S Host SMBus CLK Synth The above system block diagram shows a generic example of a clock distribution for a simple single-channel FBD Platform. Also shown are the Northbound/Southbound channels as well as SMBus Interface. ...
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Advanced Memory Buffer - Interface Block Diagram Primary or Host Direction PN0 ~ PN13 Outlink PN0# ~ PN13# PS0 ~ PS9 SB FBD PS0# ~ PS9# Inlink SDA SMBus SCL SA0 ~ SA2 Corporate Headquarters Box 1757, Fremont, ...
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AMB Pin Description FBD Channel Signals (Signal Count: 99) Pin Name Pin Description SCK Positive line of the differential pair of system clock inputs. SCK# Negative line of the differential pair of system clock inputs. PN0 ~ PN13 Primary Northbound ...
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AMB Pin Description (Contd...) DDR2 Interface Signals (Contd...) Pin Name Pin Description DDRC_C14 DDR Compensation: Common return pin for DDRC_B18 and DDRC_C18. DDRC_B18 DDR Compensation: Resistor connected to common return pin DDRC_C14. DDRC_C18 DDR Compensation: Resistor connected to common return ...
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Block Diagram RCS0# RCS1# RCKE0 RCKE1 RODT0 DQS0 DQS S# CKE ODT DQS0# DQS# DQ0 I DQ1 I/O 1 DQ2 I/O 2 DQ3 I/O 3 DQS1 DQS S# CKE ODT DQS1# DQS# DQ8 I DQ9 I/O ...
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SPD EEPROM SA0 SA0 DDSPD SA1 SA1 E1 SA2 SA2 SCL SCL SDA SDA WP ODT0, RAS#, CAS#, WE A15, BA0 ~ BA2, CK0 ~ CK3, CK0# ~ CK3# CS0#, CS1#, CKE0, CKE1 V /V ...
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Physical Dimensions 240-pin Fully Buffered DIMM R0.75 8x 9.81 20.92 3.00 1 3.90 5.175 5.00 FULL 1.50 2.50 Detail A (All dimensions are in millimeters with ±0.15mm tolerance unless specified otherwise.) Corporate Headquarters Box 1757, ...
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Physical Dimensions Full Module Front HeatSpreader 10.00 2x 2.5 5 42.102 1.02 Corporate Headquarters Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com Europe: 5 Kelvin Park South, Kelvin South, East Kilbride, ...
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Physical Dimensions Full Module Back HeatSpreader & Clip 10.00 3 14.788 42.102 1.02 Corporate Headquarters Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com Europe: 5 Kelvin Park South, Kelvin South, East ...
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Serial Presence Detect Table (SG2567FBD28451IB/SEDC) Byte No. Byte Description 0 Number of Bytes Utilized/Number of Bytes in SPD Device/CRC Coverage 1 SPD Revision 2 Key Byte 3 Voltage Levels of this assembly 4 SDRAM Addressing 5 Module Physical Attributes 6 ...
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Serial Presence Detect Table (Contd.) Byte No. Byte Description 27 Minimum Internal Write to Read Command Delay (t ) WTR 28 Minimum Internal Write to Precharge Command Delay (t ) RTP 29 Burst Lengths Supported 30 Terminations Supported 31 Drivers ...
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Serial Presence Detect Table (Contd.) Byte No. Byte Description 84 Buffer Read Access Time for DDR2-800 (AMB.LINKPARNXT[1:0] = 11) 85 Buffer Read Access Time for DDR2-667 (AMB.LINKPARNXT[1:0] = 10) 86 Buffer Read Access Time for DDR2-533 (AMB.LINKPARNXT[1:0] = 01) 87 ...
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Serial Presence Detect Table (Contd.) Byte No. Byte Description 109 AMB Personality Bytes: Post-Initialization byte 8 110 AMB Personality Bytes: Post-Initialization byte 9 111 AMB Personality Bytes: Post-Initialization byte 10 112 AMB Personality Bytes: Post-Initialization byte 11 113 AMB Personality ...
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Note: 1. Manufacturing Location: 00h - Undefined, 01h - Fremont, USA, 02h - Aguada, Puerto Rico, 03h - East Kilbride, Scotland, 04h - Penang, Malaysia, 05h - Bangalore, India, 06h - Sao Paulo, Brazil, 07h - Aguadilla, Puerto Rico, 08h ...
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Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and func- tional operation of the device at these or any other conditions above those indicated in the operational sections of this ...
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Timing Parameters Parameter EI assertion pass-through timing EI deassertion pass-through timing EI assertion duration FBD command to DDR2 clock out that latches command FBD command to DDR2 WRITE DDR2 READ to FBD (last FBDIMM) Resample pass-through time Resynch pass-through time ...
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DDR2 I Specifications and Conditions DD Symbol Parameter/Condition I Idle current, single or last FBDIMM: L0 state, idle (0 BW); CC_IDLE_0 primary channel enabled, secondary channel disabled, CKE I DD_IDLE_0 high; command and address lines stable, DDR2 SDRAM clock active. ...
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V Currents TT Description Idle current, DDR2 SDRAM device power down Active power, 50% DDR2 SDRAM BW Reference Clock Input Specifications Parameter Reference clock frequency Rise time, fall time Voltage high Voltage low Absolute crossing point Relative crossing point Percentage ...
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Notes: 1. 133MHz for PC2-4200 and 166MHz for PC2-5300. 2. Measured with SSC Disabled. 3. Measured differentially through the range of 0.175V to 0.525V. 4. The crossing point must meet the absolute and relative crossing point specification simultaneously ...
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Differential Transmitter Output Specifications Parameter Differential peak-to-peak output voltage for large voltage swing Differential peak-to-peak output voltage for regular voltage swing Differential peak-to-peak output voltage for small voltage swing DC common code output voltage for large voltage swing DC common ...
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Differential Transmitter Output Specifications (Contd.) Parameter Differential TX output rise/fall time Mismatch between rise and fall times Differential return loss Common mode return loss Transmitter termination impender D+/D- TX Impedance difference Lane-to lane skew at TX Lane-to lane skew at ...
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Notes: 1. Specified at the packaged pins into a timing and voltage compliance test load. Common mode measurements to be performed using a 101010 pattern. 2. The transmitter design should not artificially elevate the common mode in order to meet ...
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Differential Receiver Input Specifications Parameter Differential peak-to-peak input voltage for large voltage swing Maximum single ended voltage in EI condition Maximum single ended voltage in EI condition (DC only) Maximum peak-to-peak diffenrential voltage in EI condition Single ended voltage (w.r.t ...
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Differential Receiever Input Specifications Parameter Differential return loss Common mode return loss RX termination impedance D+/D- RX Impedance difference Lane-to lane PCB skew at RX Minimum RX drift tolerance Minimum data tracking 3dB bandwidth Electrical idle entry detect time Electrical ...
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Notes: 1. Specified at the package pins into a timing and voltage compliant test setup. Note that the signal levels at the pad will be lower than that at the pin. 2. Single-ended voltages below that value that are simultaneously ...
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AMB Initialization The FBD initialization process generally follows the top-to-bottom sequence of the state transitions shown in the the high level AMB Initialization Flow diagram. The host must sequence the AMB devices through the Disable, Cal- ibrate, (back to Disable), ...
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Part Number Decode S G 256 7 FBD SMART Modular Technologies 2 Module Process Technology G: Green Module (RoHS Compliant) 3 Module Address Depth 256: 256M 4 Module ...
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Disclaimer: No part of this document may be copied or reproduced in any form or by any means, or transferred to any third party, without the prior written consent of an authorized representative of SMART Modular Technologies, Inc. (“SMART”). The ...