sg2567fbd28451ibdc ETC-unknow, sg2567fbd28451ibdc Datasheet - Page 27

• Manufacturer Part Number: sg2567fbd28451ibdc
• Description: Dram Module Ddr2 Sdram 2gbyte 240fbdimm
• Manufacturer: ETC-unknow

Notes:
1. Specified at the packaged pins into a timing and voltage compliance test load. Common mode measurements
2. The transmitter design should not artificially elevate the common mode in order to meet this specification.
3. This is the ratio of the V
4. De-emphasis shall be disabled in the calibration state.
5. Includes all sources of AC common mode noise.
6. Single ended voltages below that value that are simultaneously detected on D+ and D- are interpreted as the
7. The maximum value is specified to be at least (V
8. This number does not include the effects of SSC or reference clock jitter.
9. Defined as expected maximum jitter for the given probability as measured in the system (TJ), less the
10. Pulse width measure at 0V differential.
11. One of the components that contribute to the deterioration of the return loss is the ESD structure which needs
12. The termination of small signal resistance; tolerance across voltages from 100mV to 400mV shall not exceed
13. Lane to Lane skew at the Transmitter pins for an end component.
14. Lane to Lane skew at the Transmitter pins for an intermediate component (assuming zero Lane to Lane skew
15. This is static skew. An FBDIMM component is not allowed to change its lane to lane phase relationship after
16. Measured form the reference clock edge to the center of the output eye. This specification must be met across
17. BER per differential lane.
V
V
V
R
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TX-DIFFp-p
TX-CM
TX-CM-AC
TX-MATCH-DC
to be performed using a 101010 pattern.
V
Electrical Idle condition.
unbounded jitter.
to be carefully designed.
+/-5W with regard to the average of the values measured at 100mV and 400mV for that pin.
at the Receiver pins of the incoming PORT).
initialization.
specified voltage and temperture ranges for a single component. Drift rate change is significantly below the
tracking capability of the receiver.
TX-DIFFp-p
= DC
= ((Max
= 2 x
(avg)
= 2 x ((
of the first bit aftre a transition.
⏐
of (
⏐
V
V
TX-D+
⏐
TX-D+
⏐
V
R
TX-D+
TX-D+
TX-DIFFp-p
- V
+ V
TX-D-
+ V
TX-D-
- R
TX-D-
TX-D-
⏐
(EQ1)
⏐
of the second and following bits after a transition divided by the
)/2) - ((Min
⏐
⏐
/2) (EQ2)
) / (
⏐
R
TX-D+
⏐
V
TX-DIFFp-p_L
TX-D+
+ R
TX-D-
+ V
TX-D-
⏐
/4) + V
)) (EQ4)
SG2567FBD28451UUDC
⏐
)/2) (EQ3)
TX-CM_L
+ (V
TX-CM-ACp-p
January 15, 2008
/2).
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