sg2567fbd28451ibdc ETC-unknow, sg2567fbd28451ibdc Datasheet - Page 21

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sg2567fbd28451ibdc

Manufacturer Part Number
sg2567fbd28451ibdc
Description
Dram Module Ddr2 Sdram 2gbyte 240fbdimm
Manufacturer
ETC-unknow
Datasheet
Timing Parameters
Notes:
1. Defined in FBDIMM architecture and protocol specification.
2. Clocks defined as core clocks - 2x SCK input.
3. For DDR2-667 (PC2-5300), this is measured from the beginning of the frame at the southbound input to the
4. For DDR2-667 (PC2-5300), this is measured from the latest DQS input to the AMB to the start of the matching
Assumptions for all Parameters:
Primary channel drive strength at 100 percent with de-emphasis at -6.5dB, secondary channel drive strength at 60
percent with de-emphasis at -3dB when enabled.
Address and data fields are psuedo-random, which provides a 50 percent toggle rate on DDR2 SDRAM data lines
and link lanes when data is being transferred.
Assuming 1 ACTIVATE command and 1 READ/WRITE command per BL transfer, BL = 4.
10 southbound lanes and 14 northbound lanes are enabled and active.
SPD-specific assumptions:
AMB power spec specific assumptions:
Corporate Headquarters: P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe: 5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific: Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
Parameter
EI assertion pass-through timing
EI deassertion pass-through timing
EI assertion duration
FBD command to DDR2 clock out that
latches command
FBD command to DDR2 WRITE
DDR2 READ to FBD (last FBDIMM)
Resample pass-through time
Resynch pass-through time
Bitlock interval
Framelock interval
DDR2 clock output that latches the first command of a frame to the DDR2 SDRAM devices.
data frame at the northbound FBDIMM outputs.
Number of devices on the specific FBDIMM assumed.
Termination of command, address, and control is actual value used on the FBDIMM.
ECC as per the specific FBDIMM.
SPD specifies Delta T.
Specific ECC FBDIMM assumed (72 bit data, 14 lanes northbound with DDR2 SDRAMs as defined in the con-
figuration options of this datasheet.
Modeled with 27Ω termination for command, address, and clocks, and 47Ω termination for control.
AMB specification describes current for each rail.
t
El Propogate
t
Framelock
Symbol
t
Bitlock
t
EID
t
EI
Min
100
7.1
4.0
-
-
-
-
-
-
-
SG2567FBD28451UUDC
TBD
1.25
2.25
Typ
8.1
5.0
-
-
-
-
-
Bitlock
Max
119
154
9.1
6.0
4
-
-
-
-
January 15, 2008
frames
frames
Units
CK
CK
CK
ns
ns
ns
ns
ns
Notes
1, 2
2
3
4
1
1
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