IDT72V3674L15PF IDT, Integrated Device Technology Inc, IDT72V3674L15PF Datasheet - Page 5

• Manufacturer Part Number: IDT72V3674L15PF
• Description: IC FIFO 16384X36 15NS 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3674L15PF

• Function: Asynchronous
• Memory Size: 576K (16K x 36)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Configuration: Dual
• Density: 576Kb
• Access Time (max): 10ns
• Word Size: 36b
• Organization: 8Kx36x2
• Sync/async: Synchronous
• Expandable: No
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 400mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3674L15PF

PIN DESCRIPTIONS (CONTINUED)
NOTE:
1. FS2, BM and SIZE inputs are not TTL compatible. These inputs should be tied to GND or V
IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
FS0/SD
FS1/SEN
FS2
MBA
MBB
MBF1
MBF2
MRS1
MRS2
PRS1/
RT1
PRS2/
RT2
RTM
SIZE
Symbol
(1)
(1)
Flag Offset Select 0/
Serial Data
Flag Offset Select 1/
Serial Enable,
Flag Offset Select 2
Port A Mailbox
Select
Port B Mailbox
Select
Mail1 Register
Flag
Mail2 Register
Flag
FIFO1 Master
Reset
FIFO2 Master
Reset
Partial Reset/
Retransmit FIFO1
Partial Reset/
Retransmit FIFO2
Retransmit Mode
Bus Size Select
Name
I/O
O
O
I
I
I
I
I
I
I
I
I
I
I
FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During
Master Reset, FS1/SEN and FS0/SD, together with FS2, select the flag offset programming method
Three offset register programming methods are available: automatically load one of five preset values
(8, 16, 64, 256 or 1,024), parallel load from Port A, and serial load.
When serial load is selected for flag offset register programming, FS1/SEN is used as an enable
synchronous to the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA
load the bit present on FS0/SD into the X and Y registers. The number of bit writes required to program
the offset registers is 44 for the IDT72V3654, 48 for the IDT72V3664, and 52 for the IDT72V3674.
The first bit write stores the Y-register (Y1) MSB and the last bit write stores the X-register (X2) LSB.
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When
the A0-A35 outputs are active, a HIGH level on MBA selects data from the mail2 register for output
and a LOW level selects FIFO2 output register data for output.
A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the
B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register for output and
a LOW level selects FIFO1 output register data for output.
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register.
Writes to the mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH
transition of CLKB when a Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either
a Master or Partial Reset of FIFO1.
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes
to the mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH
transition of CLKA when a Port A read is selected and MBA is HIGH. MBF2 is set HIGH following
either a Master or Partial Reset of FIFO2.
A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the
Port B output register to all zeroes. A LOW-to-HIGH transition on MRS1 selects the programming
method (serial or parallel) and one of five programmable flag default offsets for FIFO1 and FIFO2. It
also configures Port B for bus size and endian arrangement. Four LOW-to-HIGH transitions of CLKA
and four LOW-to-HIGH transitions of CLKB must occur while MRS1 is LOW.
A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets
the Port A output register to all zeroes. A LOW-to-HIGH transition on MRS2, toggled simultaneously with
MRS1, selects the programming method (serial or parallel) and one of the programmable flag default
offsets for FIFO2. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB
must occur while MRS2 is LOW.
This pin is muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM
pin. If RTM is in a LOW condition, a LOW on this pin performs a Partial Reset on FIFO1 and initializes
the FIFO1 read and write pointers to the first location of memory and sets the Port B output register to
all zeroes. During Partial Reset, the currently selected bus size, endian arrangement, programming
method (serial or parallel), and programmable flag settings are all retained. If RTM is HIGH, a LOW on
this pin performs a Retransmit and initializes the FIFO1 read pointer only to the first memory location.
This pin is muxed for both Partial Reset and Retransmit operations, it is used in conjunction with the RTM
pin. If RTM is in a LOW condition, a LOW on this pin performs a Partial Reset on FIFO2 and initializes
the FIFO2 read and write selected bus size, endian arrangement, programming method (serial or
parallel), and programmable flag settings are all retained. If RTM is HIGH, a LOW on this pin performs
a Retransmit and initializes the FIFO2 read pointer only to the first memory location.
This pin is used in conjunction with the RT1 and RT2 pins. When RTM is HIGH a Retransmit is performed
on FIFO1 or FIFO2 respectively.
A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when
BM is HIGH selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size and endian
arrangement for Port B. The level of SIZE must be static throughout device operation
TM
WITH BUS-MATCHING
5
CC
.
Description
COMMERCIAL TEMPERATURE RANGE