IDT72V3674L15PF IDT, Integrated Device Technology Inc, IDT72V3674L15PF Datasheet - Page 32

• Manufacturer Part Number: IDT72V3674L15PF
• Description: IC FIFO 16384X36 15NS 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3674L15PF

• Function: Asynchronous
• Memory Size: 576K (16K x 36)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Configuration: Dual
• Density: 576Kb
• Access Time (max): 10ns
• Word Size: 36b
• Organization: 8Kx36x2
• Sync/async: Synchronous
• Expandable: No
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 400mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3674L15PF

NOTES:
1. t
2. FIFO2 write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 2,048 for the IDT72V3654, 4,096 for the IDT72V3664, 8,192 for the IDT72V3674.
4. If Port B size is word or byte, AFB is set LOW by the last word or byte write of the long word, respectively.
NOTE:
1. If Port B is configured for word size, data can be written to the Mail1 register using A0-A17 (A18-A35 are don't care inputs). In this first case B0-B17 will have valid data (B18-B35
CLKB
CLKA
B0-B35
IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
A0-A35
ENB
AFB
ENA
CLKA edge is less than t
CLKA
W/RA
will be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0-A8 (A9-A35 are don't care inputs). In this second case, B0-B8 will
have valid data (B9-B35 will be indeterminate).
SKEW2
CLKB
MBF1
W/RB
MBA
MBB
CSA
ENA
ENB
CSB
is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge and rising
[D-(Y2+1)] Words in FIFO2
SKEW2
t
ENS2
, then AFB may transition HIGH one CLKB cycle later than shown.
Figure 26. Timing for AFB
Figure 27. Timing for Mail1 Register and MBF1
t
EN
FIFO1 Output Register
t
t
t
t
t
t
PAF
ENS2
ENH
ENS1
ENS2
ENS1
t
DS
W1
AFB
AFB
AFB when FIFO2 is Almost-Full (IDT Standard and FWFT Modes)
AFB
t
MDV
t
t
DH
t
t
t
ENH
ENH
ENH
ENH
t
t
ENS2
PMF
t
PMR
TM
WITH BUS-MATCHING
MBF1
MBF1
MBF1
MBF1 Flag (IDT Standard and FWFT Modes)
32
(D-Y2) Words in FIFO2
t
SKEW2
t
ENH
W1 (Remains valid in Mail1 Register after read)
(1)
1
t
ENS2
COMMERCIAL TEMPERATURE RANGE
t
ENH
t
PMF
2
t
PAF
t
DIS
4664 drw29
4664 drw 28