IDT72V3674L15PF IDT, Integrated Device Technology Inc, IDT72V3674L15PF Datasheet - Page 14

• Manufacturer Part Number: IDT72V3674L15PF
• Description: IC FIFO 16384X36 15NS 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V3674L15PF

• Function: Asynchronous
• Memory Size: 576K (16K x 36)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Configuration: Dual
• Density: 576Kb
• Access Time (max): 10ns
• Word Size: 36b
• Organization: 8Kx36x2
• Sync/async: Synchronous
• Expandable: No
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 400mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V3674L15PF

TABLE 4 — FIFO1 FLAG OPERATION (IDT Standard and FWFT modes)
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read
3. X1 is the Almost-Empty offset for FIFO1 used by AEB. Y1 is the Almost-Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a FIFO1 reset or port A programming.
4. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in IDT Standard mode.
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read
3. X2 is the Almost-Empty offset for FIFO2 used by AEA. Y2 is the Almost-Full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a FIFO2 reset or port A programming.
4. The ORA and IRB functions are active during FWFT mode; the EFA and FFB functions are active in IDT Standard mode.
ENA is HIGH, MBA is LOW, and EFA/ORA is HIGH (see Table 2). FIFO
reads and writes on Port A are independent of any concurrent Port B
operation.
exception that the Port B Write/Read select (W/RB) is the inverse of the Port
A Write/Read select (W/RA). The state of the Port B data (B0-B35) lines is
controlled by the Port B Chip Select (CSB) and Port B Write/Read select
(W/RB). The B0-B35 lines are in the high-impedance state when either CSB
is HIGH or W/RB is LOW. The B0-B35 lines are active outputs when CSB is
LOW and W/RB is HIGH.
transition of CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, MBB is
LOW, and FFB/IRB is HIGH. Data is read from FIFO1 to the B0-B35 outputs
by a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is HIGH, ENB
is HIGH, MBB is LOW, and EFB/ORB is HIGH (see Table 3). FIFO reads and
writes on Port B are independent of any concurrent Port A operation.
Selects and Write/Read selects are only for enabling write and read operations
TABLE 5 — FIFO2 FLAG OPERATION (IDT Standard and FWFT modes)
IDT72V3654/72V3664/72V3674 3.3V CMOS SyncBiFIFO
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
operation necessary), it is not included in the FIFO memory count.
operation necessary), it is not included in the FIFO memory count.
The Port B control signals are identical to those of Port A with the
Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH
The setup and hold time constraints to the port clocks for the port Chip
(X1+1) to [2,048-(Y1+1)]
(X2+1) to [2,048-(Y2+1)]
(2,048-Y1) to 2,047
(2,048-Y2) to 2,047
IDT72V3654
IDT72V3654
1 to X1
1 to X2
2,048
2,048
0
0
(3)
(3)
Number of Words in FIFO Memory
Number of Words in FIFO Memory
(X2+1) to [4,096-(Y2+1)]
(X1+1) to [4,096-(Y1+1)]
(4,096-Y2) to 4,095
(4,096-Y1) to 4,095
IDT72V3664
IDT72V3664
1 to X2
1 to X1
4,096
4,096
0
0
(3)
(3)
(1,2)
(1,2)
TM
(X1+1) to [8,192-(Y1+1)]
(X2+1) to [8,192-(Y2+1)]
WITH BUS-MATCHING
(8,192-Y1) to 8,191
(8,192-Y2) to 8,191
IDT72V3674
IDT72V3674
1 to X1
1 to X2
8,192
8,192
14
0
0
and are not related to high-impedance control of the data outputs. If a port enable
is LOW during a clock cycle, the port’s Chip Select and Write/Read select may
change states during the setup and hold time window of the cycle.
the next word written is automatically sent to the FIFO’s output register by the
LOW-to-HIGH transition of the port clock that sets the Output Ready flag HIGH.
When the Output Ready flag is HIGH, subsequent data is clocked to the output
registers only when a read is selected using the port’s Chip Select, Write/Read
select, Enable, and Mailbox select.
the Empty Flag to change state on the second LOW-to-HIGH transition of the
Read Clock. The data word will not be automatically sent to the output register.
Instead, data residing in the FIFO's memory array is clocked to the output
register only when a read is selected using the port’s Chip Select, Write/Read
select, Enable, and Mailbox select. Write and read timing diagrams for Port A
can be found in Figure 7 and 14. Relevant Port B write and read cycle timing
diagrams together with Bus-Matching and Endian select operations can be
found in Figures 8 through 13.
When operating the FIFO in FWFT mode and the Output Ready flag is LOW,
When operating the FIFO in IDT Standard mode, the first word will cause
(3)
(3)
EFB/ORB
EFA/ORA
H
H
H
H
Synchronized
L
Synchronized
H
H
H
H
L
to CLKB
to CLKA
COMMERCIAL TEMPERATURE RANGE
AEB
AEA
H
H
H
L
L
H
H
H
L
L
AFA
Synchronized
AFB
Synchronized
H
H
H
L
L
H
H
H
L
L
to CLKA
to CLKB
FFA/IRA
FFB/IRB
H
H
H
H
L
H
H
H
H
L