AN2109 Freescale Semiconductor / Motorola, AN2109 Datasheet - Page 9
AN2109
Manufacturer Part Number
AN2109
Description
MPC555 Interrupts
Manufacturer
Freescale Semiconductor / Motorola
Datasheet
1.AN2109.pdf
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3.1 PowerPC Core Interrupt
Decrementer
RESET
IREQ
NMI
or
The PowerPC core has only a single interrupt input, which is from the interrupt controller. See
2. This interrupt is enabled by the external interrupt enable (EE) bit in the machine state register (MSR).
Besides enabling interrupt exceptions, this bit also enables the decrementer exception.
Before recognizing the interrupt exception, all instructions being executed are completed. Once the core
recognizes any exception, hardware automatically performs a machine state saving context switch as
shown in
NOTE: The MSR[EE] bit must be set in order to allow the PowerPC processor to recognize any
interrupts.
Table
5.
SPR80
EIE
&
Freescale Semiconductor, Inc.
SPR81
EID
For More Information On This Product,
EE
Figure 2 PowerPC Core Interrupt
SPR82
Rev. 0, 26 July 2001
(without Vector Table Relocation)
MPC555 Interrupts
NRI
RI
Go to: www.freescale.com
(saves MSR value
before exception)
MSR
SSR1
Instruction Buffer
Vector Table
n+0x100
n+0x500
n+0x900
stopped instruction)
(saves address of
SSR0
PowerPC
Core
Instruction Code
Address
MOTOROLA
Exception
0XFFF0000
or external
at 0X0 or
(internal
memory)
Vector
Table
Figure
9
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