AN2109 Freescale Semiconductor / Motorola, AN2109 Datasheet - Page 10

• Manufacturer Part Number: AN2109
• Description: MPC555 Interrupts
• Manufacturer: Freescale Semiconductor / Motorola

As mentioned in
indicate non-recoverable situations. For example: an interrupt exception occurs, causing hardware to
back up the next instruction and MSR bits to SRR0:1. If SRR0:1 are not backed up somewhere and
another exception occurs, their contents are lost. Hence the original state and instruction address prior
to the interrupt is lost. As will be shown later, interrupt exception software typically will need to back up
SRR0:1 and then set MSR[RI] = 1 to indicate the state is recoverable.
The EIE, EID, and NRI special purpose registers have the sole purpose of providing a mechanism to
quickly modify the MSR[RI] and MSR[EE] bits. Any writes to these registers cause these bits to be set
or cleared as in the table below. Writing to these registers can only be done in assembler because they
are special purpose registers, not memory-mapped. Hence they are not accessible from the c language.
To access them we must use the assembly language instruction “mtspr”. For example see below and
Table
mtspr
Register/Pointer
6.
Instruction
Pointer
SRR0
SRR1
MSR
Only negate interrupt sources while MSR[EE] = 0. Software should disable inter-
rupts in the CPU core (by clearing this bit) prior to masking or disabling any inter-
rupt which might be currently pending at the CPU core.
After disabling an interrupt, sufficient time should be allowed for the negated signal
to propagate to the CPU core, prior to re-enabling interrupts. The worst case time
is an interrupt from an IMB3 module, which would be six clocks if the IMB3 is in full
speed mode (UMCR[HSPEED] = 0) or 12 clocks if the IMB3 is in half-speed mode
(UMCR[HSPEED] = 1).
Table 5 Exception Context Switch Automatically Done By Hardware
EID, r0
Section 2.6 Recoverable Exception
Gets loaded with an instruction address depending on the exception. For
interrupts and most other exceptions, it is address of the next instruction, (i.e.,
the instruction that would have been executed if the interrupt exception did not
occur).
(Previous SRR0 contents are overwritten.)
SRR1[0:15] gets loaded with information depending on exception type.
SRR1[16:31] gets loaded with MSR[16:31].
(Previous SRR1 contents are overwritten.)
Recoverable exception status bit is cleared (RI=0)
Privilege level is set to supervisor and user (PR=0)
Little-endian mode is disabled (LE=0)
Maskable exceptions are disabled, which are:
Branches to start execution at the interrupt exception “vector”. By default, this
is location 0x500 (assuming the MSR.IP bit = 0 and exception relocation is not
enabled).
– External interrupt exceptions (EE=0)
– Floating-point unit and floating point exceptions (FP=FE0=FE1=0)
– Single-step trace exceptions (SE=0)
– Branch trace (BE=0)
Freescale Semiconductor, Inc.
For More Information On This Product,
Rev. 0, 26 July 2001
; Set RI bit = 1 and EE bit = 0 in MSR
MPC555 Interrupts
Go to: www.freescale.com
NOTE
Action
[Interrupt], the purpose of the MSR[RI] bit is to
MOTOROLA
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