AN2109 Freescale Semiconductor / Motorola, AN2109 Datasheet - Page 15

• Manufacturer Part Number: AN2109
• Description: MPC555 Interrupts
• Manufacturer: Freescale Semiconductor / Motorola

3.5 UIMB Module
Now watch the PIT decrement. When it reaches 0, the PIT status bit PISCR[PS] will set, which sets the
SIPEND bit for level 0 and the interrupt code in SIVEC to level 0. The PISCR[PS] will stay set until a “1”
is written to that bit, which means SIPEND will stay active for level 0 until, (e.g., a “1” is written to that
bit). The processor does not take the interrupt exception because the MSR[EE] bit has not been set.
All interrupts from peripherals on the IMB are passed into the UIMB module. The UIMB module has an
interrupt controller function of reducing up to 32 possible interrupt levels to 8 levels. These 8 levels go
to the SIPEND register in the USIU Interupt Controller. To achieve this reduction, IMB peripheral inter-
rupt levels 7:31 all get mapped to level 7 as shown in
1. Set PITC[PITC]=0x1000 for a modulus count (gets loaded when PITR decrements passed 0)
2. Make sure PISCR[PITF]=0 to keep PIT the clock running during while the debug signal
3. Set PISCR[PIRQ] = 0x40 to set the PIT’s interrupt level to level 0
4. Enable level 0 by setting SIMASK[LVLM0]=1
5. Set PISCR[PTE]=1 to enable the PIT clock to decrement.
6. Enable PIT interrupt by setting PISCR[PIE] = 1
FREEZE is asserted. (0 is the default value from reset.)
Some interrupt sources have a freeze control bit. Generally this allows timers to
keep incrementing or decrementing if the FREEZE debug signal is asserted. The
FREEZE signal allows users to stop various clocks to aid debugging. It is active
when in debug mode, (i.e., when instructions are executed from the debug port) in-
stead of from memory.
PIT Interrupt. The steps below will generate an interrupt request at the interrupt
controller when the PIT crosses zero. We will not enable interrupts to the core in
this example. If you have an evaluation board with visibility into registers and bit
fields, this would be a simple exercise to start understanding and experimenting
with interrupts. It assumes the default clock to the PIT is used and is enabled.
Freescale Semiconductor, Inc.
For More Information On This Product,
Rev. 0, 26 July 2001
MPC555 Interrupts
Go to: www.freescale.com
EXAMPLE
NOTE
Figure
4.
MOTOROLA
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