DS26502 Maxim Integrated Products, DS26502 Datasheet - Page 60

• Manufacturer Part Number: DS26502
• Description: T1/E1/J1/64KCC BITS Element
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
HW
Mode
Bit 0: Receive Align Frame Event (RAF). (E1 only) Set every 250µs at the beginning of align frames. Used to alert the host
that Si and Sa bits are available in the RAF and RNAF registers.
Bit 1: Receive CRC4 Multiframe Event (RCMF). (E1 only) Set on CRC4 multiframe boundaries; will continue to be set
every 2ms on an arbitrary boundary if CRC4 is disabled.
Bit 2: Receive Multiframe Event (RMF)
Bit 3: Transmit Align Frame Event (TAF). (E1 only) Set every 250µs at the beginning of align frames. Used to alert the host
that the TAF and TNAF registers need to be updated.
Bit 4: Transmit Multiframe Event (TMF)
Bit 5: Receive Signaling All Zeros Event (RSA0). (E1 only) Set when over a full MF, time slot 16 contains all zeros.
Bit 6: Receive Signaling All Ones Event (RSA1). (E1 only) Set when the contents of time slot 16 contains fewer than three
zeros over 16 consecutive frames. This alarm is not disabled in the CCS signaling mode.
Bit 7: Unused
E1 Mode: Set every 2ms (regardless if CAS signaling is enabled or not) on receive multiframe boundaries. Used to
alert the host that signaling data is available.
T1 Mode: Set every 1.5ms on D4 MF boundaries or every 3ms on ESF MF boundaries.
E1 Mode: Set every 2ms (regardless if CRC4 is enabled) on transmit multiframe boundaries. Used to alert the host
that signaling data needs to be updated.
T1 Mode: Set every 1.5ms on D4 MF boundaries or every 3ms on ESF MF boundaries.
—
X
7
0
RSA1
SR4
Status Register 4
1Ah
X
6
0
RSA0
X
5
0
TMF
X
4
0
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TAF
X
3
0
RMF
X
2
0
DS26502 T1/E1/J1/64KCC BITS Element
RCMF
X
1
0
RAF
X
0
0