DS26502 Maxim Integrated Products, DS26502 Datasheet - Page 58

• Manufacturer Part Number: DS26502
• Description: T1/E1/J1/64KCC BITS Element
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
HW
Mode
Bit 0: Receive BOC Detector Change-of-State Event (RBOC). Set whenever the BOC detector sees a change of state to a
valid BOC. The setting of this bit prompts the user to read the RFDL register.
Bit 1: Receive FDL Match Event (RMTCH). Set whenever the contents of the RFDL register matches RFDLM1 or
RFDLM2.
Bit 2: TFDL Register Empty Event (TFDLE). Set when the transmit FDL buffer (TFDL) empties.
Bit 3: RFDL Register Full Event (RFDLF). Set when the receive FDL buffer (RFDL) fills to capacity.
Bit 4: RFDL Abort Detect Event (RFDLAD). Set when eight consecutive ones are received on the FDL.
Bit 5: BOC Clear Event (BOCC). Set when 30 FDL bits occur without an abort sequence.
Bit 6: Loss Of Transmit Clock Event (LOTC). Set when the signal at the TCLK pin has not transitioned for approximately
15 periods of the scaled MCLK.
Bit 7: Receive AIS-CI Event (RAIS-CI). (T1 Only) Set when the receiver detects the AIS-CI pattern as defined in ANSI
T1.403.
RAIS-CI
X
7
0
LOTC
SR3
Status Register 3
18h
X
6
0
BOCC
X
5
0
RFDLAD
X
4
0
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RFDLF
X
3
0
TFDLE
X
2
0
DS26502 T1/E1/J1/64KCC BITS Element
RMTCH
X
1
0
RBOC
X
0
0