DS26502 Maxim Integrated Products, DS26502 Datasheet
DS26502
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DS26502 Summary of contents
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... Message (SSM) can also be recovered. The transmit portion can directly interface to T1, E1, or 64KCC synchronization interfaces as well as source the SSM in T1 and E1 modes. The DS26502 can translate between any of the supported inbound synchronization clock rates to any supported outbound rate. A separate output is provided to source a 6312kHz clock. The device is controlled through a parallel, serial, or hardware controller port ...
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... Mode Configuration Register....................................................................................34 7 NTERRUPT ANDLING 7 TATUS EGISTERS 7 NFORMATION EGISTERS TABLE OF CONTENTS (T1/ ......................................................................7 ODES NLY .......................................................................................................8 ...................................................................................................8 ................................................................................................16 .............................................................................................25 www.DataSheet4U.com ..................................................................................................25 M ........................................................................................26 ODES M ..................................................................................27 ODES ...................................................................................................... ONTROLLER ODE EATURES D .....................................................................29 ESCRIPTION F D UNCTIONAL ESCRIPTION ....................................................................................................37 .......................................................................................................37 ............................................................................................... 124 DS26502 T1/E1/J1/64KCC BITS Element .........................................................28 .................................................29 ...
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... ODE ONTROLLER CRC4 M ...........................................................63 ASED ON ULTIFRAME CCESS ASED ON OUBLE www.DataSheet4U.com ......................................................................................................79 ...................................................................................................... ...........................................................................80 PTION .............................................................................................81 .............................................................................................. NTERFACE PERATION I O NTERFACE I YNCHRONIZATION NTERFACE S I YNCHRONIZATION NTERFACE ...............................................................................................102 3 of 124 DS26502 T1/E1/J1/64KCC BITS Element -F ...............................................73 RAME ............................................95 ..........................................96 PERATION O ........................................97 PERATION O .......................................97 PERATION ...
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... AC TIMING PARAMETERS AND DIAGRAMS ............................................................111 20 .......................................................................................................111 ULTIPLEXED US 20 ONMULTIPLEXED 20 ................................................................................................................117 ERIAL US 20 ECEIVE IDE 20 RANSMIT IDE 21. REVISION HISTORY ....................................................................................................123 22. PACKAGE INFORMATION ..........................................................................................124 .........................................................................................103 ............................................................................................103 ...............................................................................................106 ................................................................................................114 US ...........................................................................119 HARACTERISTICS .........................................................................121 HARACTERISTICS www.DataSheet4U.com 4 of 124 DS26502 T1/E1/J1/64KCC BITS Element ...
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... Figure 20-7. Motorola Bus Write Timing (BTS = 1 / BIS[1:0] = 01)....................................................... 116 Figure 20-8. SPI Interface Timing Diagram, CPHA = 0, BIS[1: ................................................. 118 Figure 20-9. SPI Interface Timing Diagram, CPHA = 1, BIS[1: ................................................. 118 Figure 20-10. Receive Timing, T1, E1, 64KCC Mode .......................................................................... 120 Figure 20-11. Transmit Timing, T1, E1, 64KCC Mode ......................................................................... 122 DS26502 T1/E1/J1/64KCC BITS Element LIST OF FIGURES www.DataSheet4U.com 5 of 124 ...
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... Table 19-4. Capacitance ..................................................................................................................... 109 Table 19-5. DC Characteristics............................................................................................................ 110 Table 20-1. AC Characteristics, Multiplexed Parallel Port .................................................................... 111 Table 20-2. AC Characteristics, Non-Mux Parallel Port ....................................................................... 114 Table 20-3. AC Characteristics, Serial Bus.......................................................................................... 117 Table 20-4. Receive Side AC Characteristics ...................................................................................... 119 Table 20-5. Transmit Side AC Characteristics ..................................................................................... 121 DS26502 T1/E1/J1/64KCC BITS Element LIST OF TABLES www.DataSheet4U.com 6 of 124 ...
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... Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use 1.544MHz for T1 operation § Can be placed in either the receive or transmit path or disabled § Limit trip indication DS26502 T1/E1/J1/64KCC BITS Element www.DataSheet4U.com 7 of 124 ...
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... Multiplexed or nonmultiplexed buses § Intel or Motorola formats § Supports polled or interrupt-driven environments § Software access to device ID and silicon revision § Software-reset supported with automatic clear on power-up § Hardware controller port § Hardware reset pin DS26502 T1/E1/J1/64KCC BITS Element www.DataSheet4U.com 8 of 124 ...
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... SPECIFICATIONS COMPLIANCE The DS26502 meets all applicable sections of the latest telecommunications specifications including those listed in the following tables. Table 2-1. T1-Related Telecommunications Specifications ANSI T1.102: Digital Hierarchy Electrical Interface ANSI T1.231: Digital Hierarchy–Layer 1 in Service Performance Monitoring ANSI T1.403: Network and Customer Installation Interface–DS1 Electrical Interface TR62411 (ANSI) “ ...
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... Attachment requirements for terminal equipment interface” (ITU) “Synchronous Frame Structures used at 1544, 6312, 2048, 8488, and 44,736kbps Hierarchical Levels” (ITU) “Frame Alignment and Cyclic Redundancy Check (CRC) Procedures Relating to Basic Frame Structures Defined in Recommendation G.704” DS26502 T1/E1/J1/64KCC BITS Element www.DataSheet4U.com 10 of 124 ...
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... DATA ENABLED U www.DataSheet4U.com AND DATA PATH X PARALLEL/SERIAL CPU I/F HARDWARE CONTROLLER JTDI JTDO HARDWARE CONTROLLER 11 of 124 DS26502 T1/E1/J1/64KCC BITS Element T1/E1 SSM FRAMER 64KCC DECODER T1/E1 SSM FORMATTER 64KCC CODER BIS1 BIS0 PARALLEL, SERIAL, OR RCLK LOF_CCE RSER RS_8K 400HZ TCLK ...
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... DATA CLOCK DATA LIU - DATA Figure 3-3. Transmit PLL Clock Mux Diagram TPCR.2 RECOVERED CLOCK TCLK PIN JA CLOCK (HARDWARE MODE PIN NAME) DS26502 T1/E1/J1/64KCC BITS Element JITTER ATTENUATOR ENABLED AND IN RX PATH LOCAL LOOPBACK (LBCR.3) JITTER ATTENUATOR ENABLED AND IN TX PATH ...
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... Figure 3-4. Master Clock PLL Diagram X12,X16 MULTIPLIER PLL TO CLOCK AND DATA RECOVERY ENGINE IN RECEIVE LIU DS26502 T1/E1/J1/64KCC BITS Element MCLK PIN LIC4.6 PRE-SCALER (MPS0) LIC4.7 DIVIDE (MPS1 2.048MHz to 1.544MHz PLL LIC2.3 (JACKS) (HARDWARE MODE PIN NAME) www.DataSheet4U.com 13 of 124 ...
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... FUNCTION Figure (Figure 20-11). (Figure 20-11). www.DataSheet4U.com Figure 3-1 20-11). Figure 3-1 and the transmit timing diagram Figure 3-1 and the transmit timing diagram 14 of 124 DS26502 T1/E1/J1/64KCC BITS Element Figure 3-4. Figure 3-4. 3-1, Figure 3-3, and the transmit Figure 3-1 and the transmit and the transmit timing diagram (Figure 20-11). (Figure ...
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... T1 Mode: Will toggle high when receive Blue Alarm is detected. RAIS O E1 Mode: Will toggle high when receive AIS is detected. 64KCC Mode: This pin will high-impedance state. 6312kHz Mode: This pin will high-impedance state. DS26502 T1/E1/J1/64KCC BITS Element FUNCTION www.DataSheet4U.com 15 of 124 ...
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... TMODE2 I to configure the transmit operating mode. Tri-State Control and Device Reset. A dual-function pin. A zero-to-one transition issues a hardware reset to the DS26502 register set. Configuration TSTRST I register contents are set to the default state. Leaving TSTRST high tri-states all output and I/O pins (including the parallel control port). Set low for normal operation ...
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... AD[0]. TCSS0: Transmit Clock Source Select 0. MISO: In serial bus mode (BIS[1:0] = 10), this pin serves as the serial data output Master In-Slave Out. TCSS1 Transmit Clock Source Select. Transmit Clock Source Select 1 I DS26502 T1/E1/J1/64KCC BITS Element FUNCTION www.DataSheet4U.com 17 of 124 ...
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... In multiplexed bus operation (BIS[1:0] = 00), these pins are not used and I should be tied low. TAIS: When set and in T1/E1 operating modes, the transmitter will transmit an AIS pattern. This pin is ignored in all other operating modes. DS26502 T1/E1/J1/64KCC BITS Element FUNCTION www.DataSheet4U.com 18 of 124 ...
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... PLL. Write Input (Read/Write)/Transmit Mode Select 3 WR (R/W)/ WR: In Processor Mode, this pin is the active-low write signal. I TMODE3 TMODE3: In Hardware Mode, this pin selects the transmit-side operating mode. DS26502 T1/E1/J1/64KCC BITS Element FUNCTION www.DataSheet4U.com 19 of 124 ...
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... T1 and E1 modes. MCLK I The clock rate can be 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When using the DS26502 in T1-only operation, a 1.544MHz (50ppm) clock source can be used. Receive Tip. Analog input for clock recovery circuitry. This pin connects via a RTIP I 1:1 transformer to the network ...
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... Digital Signal Ground. 0.0V. Should be tied to the RVSS and TVSS pins. Receive Analog Signal Ground. 0.0V. Should be tied to the DVSS and TVSS RVSS — pins. Transmit Analog Signal Ground. 0.0V. Should be tied to the DVSS and TVSS — RVSS pins. DS26502 T1/E1/J1/64KCC BITS Element FUNCTION www.DataSheet4U.com 21 of 124 ...
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... Hardware Mode: MCLK Prescaler Select 0 Parallel Port Mode: Address Latch Enable/Address Bus Bit 7 — MPS1 Serial Port Mode: Unused, should be connected to V Hardware Mode: MCLK Prescaler Select 1 TCLK TCLK External Transmit Clock Input 22 of 124 DS26502 T1/E1/J1/64KCC BITS Element FUNCTION . ...
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... Transmit Analog Ring Output Parallel Port Mode: Bus Type Select (Motorola/Intel) Serial Port Mode: Unused, should be connected to V — HBE Hardware Mode: Receive and Transmit DB3/B8ZS Enable BIS0 BIS0 Bus Interface Select Mode 124 DS26502 T1/E1/J1/64KCC BITS Element FUNCTION . . . . ...
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... Serial Port Mode: Serial Data Out (Master In-Slave MIS0 TCSS0 Out) Hardware Mode: Transmit Clock Source Select 0 Parallel Port Mode: Address/Data Bus Bit 1 MOSI RMODE3 Serial Port Mode: Serial Data In (Master Out-Slave In) Hardware Mode: Receive Mode Select 3 www.DataSheet4U.com 24 of 124 DS26502 T1/E1/J1/64KCC BITS Element FUNCTION . ...
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... E1 modes is selected and internal termination is enabled selected for E1TS both transmit and receive, then both terminations will be the same. PIN 75W 1 = 120W TRANSMIT CLOCK SOURCE www.DataSheet4U.com FUNCTION 25 of 124 DS26502 T1/E1/J1/64KCC BITS Element Table 6-1. The PLL_OUT pin is always ...
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... E1 CAS and CRC4 0 E1 G.703 2048kHz Synchronization Interface 1 64kHz + 8kHz Synchronization Interface 0 64kHz + 8kHz + 400Hz Synchronization Interface 1 6312kHz Synchronization Interface 124 DS26502 T1/E1/J1/64KCC BITS Element RETURN LOSS Rt (1) N.M. 0 N.M. 0 21dB 6.2Ω 21dB 11.6Ω — — — — ...
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... The DS26502 does not have an internal source for CAS signaling and multiframe alignment generation. CAS Note 1: signaling, and the multiframe alignment word, must be embedded in the transmit data (in the TS16 position) present on the TSER pin and frame aligned to sync signal on the TS_8K_4 pin. ...
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... Remote Loopback Enable: In this loopback, data input to the framer portion of the DS26502 will be transmitted back to the transmit portion of the LIU. Data will continue RLB to pass through the receive side framer of the DS26502 as it would normally and the data PIN 60 from the transmit side formatter will be ignored. ...
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... MOSI and MISO) and a chip select (CS), with the DS26502 acting as the slave. Port read/write timing is not related to the system read/write timing, thus allowing asynchronous, half-duplex operation. See the AC Electrical Characteristics section for the AC timing characteristics of the serial port ...
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... R/W bit, the target register address, and the Burst bit. After these two control bytes, the DS26502 responds with the requested data byte. After the first data byte, if the Burst bit is set, the DS26502 auto-increments its address counter and transmits the byte stored in the next higher address location ...
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... Reserved 40 R/W Transmit Align Frame Register 41 R/W Transmit Non-Align Frame Register 42 R/W Transmit Si Align Frame 43 R/W Transmit Si Non-Align Frame REGISTER NAME www.DataSheet4U.com 31 of 124 DS26502 T1/E1/J1/64KCC BITS Element REGISTER ABBREVIATION TSTRREG IOCR1 IOCR2 T1RCR1 T1RCR2 T1TCR1 T1TCR2 T1CCR MCREG TPCR — — — — ...
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... Test Register 13 FD R/W Test Register 14 FE R/W Test Register 15 FF R/W Test Register 16 *TEST1 to TEST16 registers are used only by the factory. REGISTER NAME www.DataSheet4U.com 32 of 124 DS26502 T1/E1/J1/64KCC BITS Element REGISTER ABBREVIATION TRA TSa4 TSa5 TSa6 TSa7 TSa8 TSACR — RFDL TFDL RFDLM1 RFDLM2 — ...
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... Bits Unused, must be set = 0 for proper operation. Bits 4 and 5: Test Mode Bits (TEST0, TEST1). Test modes are used to force the output pins of the DS26502 into known states. This can facilitate the checkout of assemblies during the manufacturing process and also be used to isolate devices from shared buses ...
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... Synchronization Interface www.DataSheet4U.com 1 0 64kHz + 8kHz + 400Hz Synchronization Interface 1 1 6312kHz Synchronization Interface 124 DS26502 T1/E1/J1/64KCC BITS Element RMODE2 RMODE1 RMODE0 RMODE2 RMODE1 RMODE0 PIN 61 PIN 4 PIN ESF J1 D4 ...
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... Note 1: The DS26502 does not have an internal source for CAS signaling and multiframe alignment generation. CAS signaling, and the multiframe alignment word, must be embedded in the transmit data (in the TS16 position) present on the TSER pin and frame aligned to sync signal on the TS_8K_4 pin. ...
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... Bits 6 and 7: Transmit PLL Output Frequency Select (TPLLOFS[1:0]). These bits are used to select the TX PLL output frequency. TPLLOFS1 TPLLOFS0 Input Frequency 1.544MHz 2.048MHz 64kHz 6312kHz Output Frequency 1.544MHz 2.048MHz 64kHz 6312kHz www.DataSheet4U.com 36 of 124 DS26502 T1/E1/J1/64KCC BITS Element Figure 3-3. ...
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... The user will always precede a read of any of the status registers with a write. The byte written to the register will inform the DS26502 which bits the user wishes to read and have cleared. The user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and a zero in the bit positions he or she does not wish to obtain the latest information on ...
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... Status Register 1 interrupt active. Bit 3: Status Register 4 (SR4 Status Register 1 interrupt not active Status Register 1 interrupt active. Bits Unused — — SR4 SR3 www.DataSheet4U.com 38 of 124 DS26502 T1/E1/J1/64KCC BITS Element 1 0 SR2 SR1 ...
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... T1 FRAMER/FORMATTER CONTROL REGISTERS The T1 framer portion of the DS26502 is configured via a set of five control registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS26502 has been initialized, the control registers will only need to be accessed when there is a change in the system configuration ...
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... Japanese standard JT–G704 CRC6 calculation Bits Unused, must be set = 0 for proper operation. Bit 5: Receive B8ZS Enable (RB8ZS B8ZS disabled 1 = B8ZS enabled RB8ZS — — HBE 0 0 PIN55 www.DataSheet4U.com 40 of 124 DS26502 T1/E1/J1/64KCC BITS Element — RJC RD4YM ...
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... F bits sampled at TSER Bit 7: Transmit Japanese CRC6 Enable (TJC use ANSI/AT&T/ITU CRC6 calculation (normal operation use Japanese standard JT–G704 CRC6 calculation TCPT — — www.DataSheet4U.com 41 of 124 DS26502 T1/E1/J1/64KCC BITS Element — — TYEL ...
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... Fs pattern from the TFDL register. In all other modes this bit must be set = Fs-bit insertion disabled 1 = Fs-bit insertion enabled Bit 7: Transmit B8ZS Enable (TB8ZS B8ZS disabled 1 = B8ZS enabled — FBCT2 FBCT1 TD4YM www.DataSheet4U.com 42 of 124 DS26502 T1/E1/J1/64KCC BITS Element — TB7ZS ...
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... ANSI T1.403: No more than 15 consecutive zeros and at least N ones in each and every time window bits, where through 23. When this bit is set to one, the DS26502 forces the transmitted stream to meet this requirement no matter the content of the transmitted stream. When running B8ZS, this bit should be set to zero, as B8ZS encoded data streams cannot violate the pulse-density requirements ...
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... Note: The definition of Blue Alarm (or Alarm Indication Signal unframed, all-ones signal. Blue Alarm detectors should be able to operate properly in the presence of a 10E-3 error rate, and they should not falsely trigger on a framed, all-ones signal. The Blue Alarm criteria in the DS26502 has been set to achieve this performance. SET CRITERIA ...
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... E1 FRAMER/FORMATTER CONTROL REGISTERS The E1 framer portion of the DS26502 is configured via a set of two control registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS26502 has been initialized, the control registers will only need to be accessed when there is a change in the system configuration ...
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... CRC4 code words out of 1000 received in error Two consecutive MF alignment words received in error — TSiS — — www.DataSheet4U.com 124 DS26502 T1/E1/J1/64KCC BITS Element ITU SPEC. G.706 4.1.1 4.1.2 G.706 4.2 and 4.3.2 G.732 5 THDB3 — HBE 0 0 PIN 55 ...
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... CSC1 is omitted to allow resolution to >400ms using 5 bits — — — CRCRC www.DataSheet4U.com CSC3 CSC2 CSC0 FASSA 124 DS26502 T1/E1/J1/64KCC BITS Element FASRC CASRC CASSA CRC4SA ...
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... Bits Chip Revision Bits (ID0 to ID3). The lower four bits of the IDR are used to display the die revision of the chip. IDO is the LSB of a decimal code that represents the chip revision. Bits Device ID (ID4 to ID7). The upper four bits of the IDR are used to display the DS26502 ID. The DS26502 ID is 0000. ...
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... X Mode Bit 0: Receive Loss of Frame Condition (RLOF). Set when the DS26502 is not synchronized to the received data stream. Bit 1: Receive Loss Of Signal Condition (RLOS). Set when 255 (or 2048 if E1RCR mode or 192 T1 mode consecutive zeros have been detected. In 6312kHz Synchronization Interface Mode, this bit will be set when the signal received is out of range as defined by the G ...
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... Bit 6: Receive Alarm Indication Signal Clear Event (RAISC interrupt masked 1 = interrupt enabled Bit 7: Receive Yellow Alarm Clear Event (RYELC interrupt masked 1 = interrupt enabled RLOSC RLOFC RYEL www.DataSheet4U.com 50 of 124 DS26502 T1/E1/J1/64KCC BITS Element RAIS RLOS RLOF ...
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... RS_8K outputs CAS multiframe boundaries 1 = RS_8K outputs CRC4 multiframe boundaries Bit 7: Unused, must be set = 0 for proper operation RSMS1 RLOFF CSM_TSDW RSM 0 0 PIN 1 Table 10-1. www.DataSheet4U.com Table 10- 124 DS26502 T1/E1/J1/64KCC BITS Element TSM TSIO ODF TSM 0 0 PIN 2 Table 10-1. ...
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... Frame sync input 0 1 Frame sync output 1 0 Multiframe sync input 1 1 Multiframe sync output 0 0 8kHz input reference 0 1 8kHz output reference 0 0 400Hz input reference 0 1 400Hz output reference Indicate loss of frame www.DataSheet4U.com 52 of 124 DS26502 T1/E1/J1/64KCC BITS Element ...
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... Bit 5: RS_8K Invert (RS_8KINV inversion 1 = invert Bit 6: TCLK Invert (TCLKINV inversion 1 = invert Bit 7: RCLK Invert (RCLKINV inversion 1 = invert RS_8KINV — TS_8K_4INV www.DataSheet4U.com 53 of 124 DS26502 T1/E1/J1/64KCC BITS Element — — — ...
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... Reserved For Network Synchronization Use 11.1 T1 Bit-Oriented Code (BOC) Controller The DS26502 contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1 mode. In typical BITS applications, the BOC controller would be used to transmit and receive Synchronization Status Messages in T1 mode over the data link. ...
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... Set integration time via BOCC.1 and BOCC.2. 2) Enable the receive BOC function (BOCC.4 = 1). 3) Enable interrupt (IMR3.0 = 1). 4) Wait for interrupt to occur. 5) Read the RFDL register. 6) The lower six bits of the RFDL register is the message. DS26502 T1/E1/J1/64KCC BITS Element www.DataSheet4U.com 55 of 124 ...
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... BOC function enabled. The RFDL register will report BOC messages Bits Unused, must be set = 0 for proper operation — RBOCE RBR RBF1 SEQUENCE IDENTIFICATION None www.DataSheet4U.com 56 of 124 DS26502 T1/E1/J1/64KCC BITS Element RBF0 SBOC ...
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... Bit 7: Receive FDL Match Bit 7 (RFDLM7). MSB of the FDL Match Code RBOC5 RBOC4 RBOC3 RBOC2 www.DataSheet4U.com RFDLM5 RFDLM4 RFDLM3 124 DS26502 T1/E1/J1/64KCC BITS Element RBOC1 RBOC0 RFDLM2 RFDLM1 RFDLM0 ...
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... MCLK. Bit 7: Receive AIS-CI Event (RAIS-CI). (T1 Only) Set when the receiver detects the AIS-CI pattern as defined in ANSI T1.403 BOCC RFDLAD RFDLF www.DataSheet4U.com 58 of 124 DS26502 T1/E1/J1/64KCC BITS Element TFDLE RMTCH RBOC ...
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... Bit 6: Loss Of Transmit Clock Event (LOTC interrupt masked 1 = interrupt enabled Bit 7: Receive AIS-CI Event (RAIS-CI interrupt masked 1 = interrupt enabled BOCC RFDLAD RFDLF www.DataSheet4U.com 59 of 124 DS26502 T1/E1/J1/64KCC BITS Element TFDLE RMTCH RBOC ...
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... Bit 6: Receive Signaling All Ones Event (RSA1). (E1 only) Set when the contents of time slot 16 contains fewer than three zeros over 16 consecutive frames. This alarm is not disabled in the CCS signaling mode. Bit 7: Unused RSA0 TMF TAF www.DataSheet4U.com 60 of 124 DS26502 T1/E1/J1/64KCC BITS Element RMF RCMF RAF ...
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... Bit 6: Receive Signaling All Ones Event (RSA1 interrupt masked 1 = interrupt enabled Bit 7: Unused, must be set = 0 for proper operation RSA0 TMF TAF www.DataSheet4U.com 61 of 124 DS26502 T1/E1/J1/64KCC BITS Element RMF RCMF RAF ...
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... Bit 4: Transmit FDL Bit 4 (TFDL4) Bit 5: Transmit FDL Bit 5 (TFDL5) Bit 6: Transmit FDL Bit 6 (TFDL6) Bit 7: Transmit FDL Bit 7 (TFDL7). MSB of the transmit FDL code TFDL5 TFDL4 TFDL3 www.DataSheet4U.com 62 of 124 DS26502 T1/E1/J1/64KCC BITS Element TFDL2 TFDL1 TFDL0 ...
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... E1 SYNCHRONIZATION STATUS MESSAGE The DS26502 provides access to both the transmit and receive Sa/Si bits. In E1, the Sa bits are used to transmit and receive the SSM. The primary method to access the Sa (and Si) bits is based on CRC4 multiframe access. An alternate method is based on double-frame access. Table 12-1. E1 SSM Messages ...
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... Bit 6: Si Bit of Frame 3(SiF3) Bit 7: Si Bit of Frame 1(SiF1 SiF4 SiF6 SiF8 SiF10 www.DataSheet4U.com SiF5 SiF7 SiF9 SiF11 124 DS26502 T1/E1/J1/64KCC BITS Element SiF12 SiF14 SiF13 SiF15 ...
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... Bit 6: Sa4 Bit of Frame 3(RSa4F3) Bit 7: Sa4 Bit of Frame 1(RSa4F1 RRAF5 RRAF7 RRAF9 RRAF11 www.DataSheet4U.com RSa4F5 RSa4F7 RSa4F9 RSa4F11 124 DS26502 T1/E1/J1/64KCC BITS Element RRAF13 RRAF15 RSa4F13 RSa4F15 ...
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... Bit 6: Sa6 Bit of Frame 3(RSa6F3) Bit 7: Sa6 Bit of Frame 1(RSa6F1 RSa5F5 RSa5F7 RSa5F9 RSa5F11 www.DataSheet4U.com RSa6F5 RSa6F7 RSa6F9 RSa6F11 124 DS26502 T1/E1/J1/64KCC BITS Element RSa5F13 RSa5F15 RSa6F13 RSa6F15 ...
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... Bit 6: Sa8 Bit of Frame 3(RSa8F3) Bit 7: Sa8 Bit of Frame 1(RSa8F1 RSa7F5 RSa7F7 RSa7F9 RSa7F11 www.DataSheet4U.com RSa8F5 RSa8F7 RSa8F9 RSa8F11 124 DS26502 T1/E1/J1/64KCC BITS Element RSa7F13 RSa7F15 RSa8F13 RSa8F15 ...
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... Bit 6: Si Bit of Frame 3(TsiF3) Bit 7: Si Bit of Frame 1(TsiF1 TsiF4 TsiF6 TsiF8 TsiF10 www.DataSheet4U.com TsiF5 TsiF7 TsiF9 TsiF11 124 DS26502 T1/E1/J1/64KCC BITS Element TsiF12 TsiF14 TsiF13 TSiF15 ...
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... Bit 6: Sa4 Bit of Frame 3(TSa4F3) Bit 7: Sa4 Bit of Frame 1(TSa4F1 TRAF5 TRAF7 TRAF9 TRAF11 www.DataSheet4U.com TSa4F5 TSa4F7 TSa4F9 TSa4F11 124 DS26502 T1/E1/J1/64KCC BITS Element TRAF13 TRAF15 TSa4F13 TSa4F15 ...
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... Bit 6: Sa6 Bit of Frame 3(TSa6F3) Bit 7: Sa6 Bit of Frame 1(TSa6F1 TSa5F5 TSa5F7 TSa5F9 TSa5F11 www.DataSheet4U.com TSa6F5 TSa6F7 TSa6F9 TSa6F11 124 DS26502 T1/E1/J1/64KCC BITS Element TSa5F13 TSa5F15 TSa6F13 TSa6F15 ...
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... Bit 6: Sa8 Bit of Frame 3(TSa8F3) Bit 7: Sa8 Bit of Frame 1(TSa8F1 TSa7F5 TSa7F7 TSa7F9 TSa7F11 www.DataSheet4U.com TSa8F5 TSa8F7 TSa8F9 TSa8F11 124 DS26502 T1/E1/J1/64KCC BITS Element TSa7F13 TSa7F15 TSa8F13 TSa8F15 ...
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... TSiAF register into the transmit data stream 1 = insert data from the TSiAF register into the transmit data stream Sa4 Sa5 Sa6 www.DataSheet4U.com 72 of 124 DS26502 T1/E1/J1/64KCC BITS Element Sa7 Sa8 ...
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... Bit 5: Frame Alignment Signal Bit 5 (FAS5). In normal operation this bit will Bit 6: Frame Alignment Signal Bit 6 (FAS6). In normal operation this bit will Bit 7: International Bit (Si FAS5 FAS4 FAS3 FAS2 www.DataSheet4U.com 124 DS26502 T1/E1/J1/64KCC BITS Element FAS1 FAS0 ...
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... Bit 6: Frame Alignment Signal Bit (0) Bit 7: International Bit (Si Sa4 Sa5 Sa6 www.DataSheet4U.com 124 DS26502 T1/E1/J1/64KCC BITS Element 1 0 Sa7 Sa8 ...
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... Bit 3: Additional Bit 5 (Sa5) Bit 4: Additional Bit 4 (Sa4) Bit 5: Remote Alarm (used to transmit the alarm A) Bit 6: Frame Nonalignment Signal Bit (1) Bit 7: International Bit (Si Sa4 Sa5 Sa6 www.DataSheet4U.com 75 of 124 DS26502 T1/E1/J1/64KCC BITS Element 1 0 Sa7 Sa8 0 0 ...
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... LINE INTERFACE UNIT (LIU) The LIU in the DS26502 contains three sections: the receiver, which handles clock and data recovery; the transmitter, which generates waveshapes and drives the network line; and the jitter attenuator. These three sections are controlled by the line interface control registers (LIC1–LIC4), which are described below. ...
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... The DS26502’s LIU is designed to be fully software selectable for E1 and T1 without the need to change any external resistors for the receive-side. The receiver will allow the user to configure the DS26502 for 75Ω ...
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... MCLK, the TCLK pin or the TX PLL. See the TX PLL clock mux diagram in Figure 3-3. Due to the nature of the design of the transmitter in the DS26502, very little jitter (less than 0.005UI broadband from 10Hz to 100kHz) is added to the jitter present on the selected transmit clock P-P source ...
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... T1 applications. Setting JACKS (LIC2. logic 0 bypasses this PLL. 13.5 Jitter Attenuator The jitter attenuator is only available in T1 and E1 modes. The DS26502’s jitter attenuator can be set to a depth of either 32 bits or 128 bits via the JABDS bit (LIC1.2). The 128-bit mode is used in applications where large excursions of wander are expected ...
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... Status Register 1 (SR1.4). 13.6 CMI (Code Mark Inversion) Option The DS26502 provides a CMI interface for connection to optical transports. This interface is a unipolar 1T2B type of signal. Ones are encoded as either a logical one or zero level for the full duration of the clock period. Zeros are encoded as a zero-to-one transition at the middle of the clock period. ...
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... TT1 of LIC4 register must be set to zero in this configuration EGL JAS JABDS PIN 11 www.DataSheet4U.com N (1) RETURN LOSS 1:2 1:2 1:2 1 124 DS26502 T1/E1/J1/64KCC BITS Element DJA TPD (1) N.M. 0 N.M. 0 21dB 6.2Ω 21dB 11.6Ω ...
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... DS26502 T1/E1/J1/64KCC BITS Element Rt (1) N.M. 0 N.M. 0 N.M. 0 N. GC2 GC1 GC0 GC1 GC0 ...
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... Normally this bit is only toggled on power-up. Must be cleared and set again for a subsequent reset. Bit 7: Unused, must be set = 0 for proper operation IBPV TAIS JACKS RCCFE TAIS JACKS 0 PIN 10 PIN 46 www.DataSheet4U.com 83 of 124 DS26502 T1/E1/J1/64KCC BITS Element SCLD CLDS ...
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... CMI normal at TTIP and RTIP 1 = invert CMI signal at TTIP and RTIP Bit 7: CMI Enable (CMIE disable CMI mode 1 = enable CMI mode — MM1 MM0 www.DataSheet4U.com 84 of 124 DS26502 T1/E1/J1/64KCC BITS Element — — TAOZ ...
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... INTERNAL RECEIVE INTERNAL TRANSMIT www.DataSheet4U.com MPS0 JACKS (LIC2. MPS0 JACKS (LIC2. 124 DS26502 T1/E1/J1/64KCC BITS Element RT2 RT1 RT0 — — — ...
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... RL3 RL2 RL0 RECEIVE LEVEL (dB) 0 Greater than -2.5 1 -2.5 to -5.0 0 -5.0 to -7.5 1 -7.5 to -10.0 0 -10.0 to -12.5 1 -12.5 to -15.0 0 -15.0 to -17.5 1 -17.5 to -20.0 0 -20.0 to -22.5 1 -22.5 to -25.0 0 -25.0 to -27.5 1 -27.5 to -30.0 0 -30.0 to –32.5 1 -32.5 to -35.0 0 -35.0 to -37.5 www.DataSheet4U.com 1 Less than -37 124 DS26502 T1/E1/J1/64KCC BITS Element RL1 RL0 ...
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... Bit 4: Jitter Attenuator Limit Trip Event (JALT). Set when the jitter attenuator FIFO reaches to within 4 bits of its useful limit. Will be cleared when read. Useful for debugging jitter-attenuation operation. Note: The jitter attenuator is only available in T1 and E1 modes — JALT — TCLE www.DataSheet4U.com 87 of 124 DS26502 T1/E1/J1/64KCC BITS Element TOCD — ...
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... Bit 4: Jitter Attenuator Limit Trip Event (JALT interrupt masked 1 = interrupt enabled — JALT — TCLE www.DataSheet4U.com 88 of 124 DS26502 T1/E1/J1/64KCC BITS Element TOCD — ...
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... Some T1 (never in E1) applications source or sink power from the network-side center taps of Note 3: the Rx/Tx transformers. Note 4: A list of transformer part numbers and manufacturers is available by contacting telecom.support@dalsemi.com. DS26502 T1/E1/J1/64KCC BITS Element www.DataSheet4U.com DESCRIPTION 89 of 124 ...
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... Some T1 (never in E1) applications source or sink power from the network-side center taps of the Rx/Tx transformers. The ground trace connected to the S2/S3 pair and the S4/S5 pair should be at least 50 mils wide Note 5: to conduct the extra current from a longitudinal power-cross event. DS26502 T1/E1/J1/64KCC BITS Element www.DataSheet4U.com DESCRIPTION 90 of 124 ...
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... MAXIMUM CURVE UI -0.77 -0.39 -0.27 -0.27 -0.12 0.00 0.27 0.35 0.93 1.16 T1.102/87, T1.403, CB 119 (Oct. 79), & I.431 Template -400 -300 -200 -100 0 100 200 300 TIME (ns 124 DS26502 T1/E1/J1/64KCC BITS Element 269ns G.703 Template 100 150 200 250 MINIMUM CURVE Time Amp. UI Time Amp. -500 0.05 -0.77 -500 -0.05 -255 0.05 -0.23 -150 -0.05 -175 0.80 -0.23 -150 0 ...
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... Figure 13-8. Jitter Tolerance (T1 Mode) 1K 100 10 1 0.1 1 Figure 13-9. Jitter Tolerance (E1 Mode) 1k 100 0.1 1 DS26502 Tolerance TR 62411 (Dec. 90) ITU-T G.823 10 100 1K FREQUENCY (Hz) www.DataSheet4U.com DS26502 Tolerance 1.5 Minimum Tolerance Level as per ITU G.823 20 10 100 1k FREQUENCY (Hz 124 DS26502 T1/E1/J1/64KCC BITS Element 10K 100K 0.2 2.4k 18k 10k 100k ...
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... Figure 13-11. Jitter Attenuation (E1 Mode) 0dB -20dB -40dB -60dB 1 DS26502 T1 MODE 10 100 1K FREQUENCY (Hz) www.DataSheet4U.com TBR12 Prohibited Area Prohibited Area DS26502 E1 MODE 10 100 1K FREQUENCY (Hz 124 DS26502 T1/E1/J1/64KCC BITS Element TR 62411 (Dec. 90) Prohibited Area 10K 100K ITU G.7XX 10K 100K ...
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... Bit 2: Remote Loopback (RLB). In this loopback, data received at RTIP and RRING will be looped back to the transmit LIU. Received data will continue to pass through the receive side framer of the DS26502 as it would normally and the data from the transmit side formatter will be ignored. ...
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... Signal format a) AMI with 8kHz bipolar violation, b) AMI with 8kHz bipolar violation removed at every 400Hz Alarm condition Alarm should not be occurred against the amplitude ranged 0.63-1.1 V 0-P Violation Violation 125 us 125 us www.DataSheet4U.com 95 of 124 DS26502 T1/E1/J1/64KCC BITS Element No Violation Violation 125 us ...
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... Table 15-2. Specification of 64kHz Clock Signal at Output Port Frequency a) 64kHz + 8kHz or b) 64kHz + 8kHz + 400Hz Load impedance 110W resistive Transmission media Symmetric pair cable Pulse width (FWHM) £ 7.8 ± 0.78ms Amplitude £1 V 0-P ± 0.1 V www.DataSheet4U.com 96 of 124 DS26502 T1/E1/J1/64KCC BITS Element ...
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... SYNCHRONIZATION INTERFACE The DS26502 has a 6312kHz Synchronization Interface mode of operation that conforms with Appendix II.2 of G.703, with the exception that the DS26502 transmits a square wave as opposed to the sine wave that is defined in the G.703 specification. 16.1 Receive 6312kHz Synchronization Interface Operation On the receive interface, a 6312kHz sine wave is accepted conforming to the input port requirements of G ...
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... JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT The DS26502 supports the standard IEEE 1149.1 instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. The DS26502 contains the following as required by IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture: § ...
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... A falling edge on JTCLK while in the update-DR state will latch the data from the shift register path of the test registers into the data output latches. This prevents changes at the parallel output due to changes in the shift register. DS26502 T1/E1/J1/64KCC BITS Element www.DataSheet4U.com 99 of 124 ...
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... JTCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising edge on JTCLK with JTMS LOW, will put the controller in the run-test-idle state. With JTMS HIGH, the controller will enter the select-DR-scan state. DS26502 T1/E1/J1/64KCC BITS Element www.DataSheet4U.com 100 of 124 ...
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... Idle 1 1 Select DR-Scan Capture DR Capture IR 0 Shift Exit DR 0 Pause Exit2 DR 1 Update DR www.DataSheet4U.com 1 0 101 of 124 DS26502 T1/E1/J1/64KCC BITS Element 1 Select IR-Scan 0 0 Shift Exit IR 0 Pause Exit2 IR 1 Update ...
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... All digital outputs of the device will be placed in a high-impedance state. The BYPASS register will be connected between JTDI and JTDO. SELECTED REGISTER Boundary Scan Bypass Boundary Scan Bypass Bypass Device Identification www.DataSheet4U.com 102 of 124 DS26502 T1/E1/J1/64KCC BITS Element INSTRUCTION CODES 010 111 000 011 100 001 ...
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... IEEE 1149.1 requires a minimum of two test registers: the bypass register and the boundary scan register. An optional test register has been included with the DS26502 design. This test register is the identification register and is used with the IDCODE instruction and the test-logic-reset state of the TAP controller ...
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... RLOS observe_only 18 TCSS1 observe_only 19 RLOF_CCE observe_only 20 RAIS observe_only 21 RSER observe_only 22 OUT_400HZ observe_only 23 RS_8K observe_only 24 RCLK observe_only 25 TS_8K_4 26 TS_8K_4_CTRL 27 TSER observe_only 28 TPOSO observe_only CONTROL TYPE CELL Output3 1 Controlr Output3 3 Controlr www.DataSheet4U.com Output3 15 Controlr Output3 26 Controlr 104 of 124 DS26502 T1/E1/J1/64KCC BITS Element ...
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... TCLK observe_only 32 ALE_A7 observe_only 33 A6 observe_only 34 A5 observe_only 35 A4 observe_only 36 A3 observe_only 37 A2 observe_only 38 A1 observe_only 39 A0 observe_only 40 AD7 41 AD6 42 AD5 43 AD4 44 AD3 45 AD2 CONTROL TYPE CELL Output3 1 Output3 1 Output3 1 Output3 1 www.DataSheet4U.com Output3 1 Output3 1 105 of 124 DS26502 T1/E1/J1/64KCC BITS Element ...
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... LSB MSB www.DataSheet4U.com LSB MSB LSB MSB 106 of 124 DS26502 T1/E1/J1/64KCC BITS Element B LSB MSB B LSB MSB B LSB MSB D0 LSB D0 ...
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... LSB MSB LSB MSB www.DataSheet4U.com LSB MSB 107 of 124 DS26502 T1/E1/J1/64KCC BITS Element A0 B LSB MSB LSB MSB LSB ...
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... Figure 18-8. SPI Serial Port Access, Write Mode, CPOL = 1, CPHA = 1 SCK CS MOSI MSB MISO LSB MSB LSB MSB www.DataSheet4U.com 108 of 124 DS26502 T1/E1/J1/64KCC BITS Element LSB MSB LSB MSB D0 LSB D0 LSB ...
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... Voltage Range on Any Pin Relative to Ground………………………………………………………-1.0V to +6.0V Operating Temperature Range for DS26502L…………………………………………………………0°C to +70°C Operating Temperature Range for DS26502LN… ...
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... Table 19-5. DC Characteristics (V = 3.3V ±5 0°C to +70°C for DS26502L DS26502LN.) PARAMETER SYMBOL Supply Current Input Leakage Output Leakage Output Current (2.4V) Output Current (0.4V) 0.0V < V < V Note Note 6: Applied to INT when tri-stated. = 3.3V ±5 MIN TYP -1 -1 +4.0 OL www ...
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... AC TIMING PARAMETERS AND DIAGRAMS Capacitive test loads are 40pF for bus signals and 20pF for all others. 20.1 Multiplexed Bus Table 20-1. AC Characteristics, Multiplexed Parallel Port = 3.3V ±5 0°C to +70°C for DS26502L DS26502LN.) PARAMETER Cycle Time Pulse Width, DS Low or RD High ...
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... Figure 20-2. Intel Bus Write Timing (BTS = 0 / BIS[1:0] = 00) ALE t ASD RD t ASD AD0-AD7 t CYC PW ASH t ASED t ASD ASL t DDR t AHL t CYC www.DataSheet4U.com PW ASH t ASED ASL t AHL 112 of 124 DS26502 T1/E1/J1/64KCC BITS Element DHR DHW t DSW ...
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... Figure 20-3. Motorola Bus Timing (BTS = 1 / BIS[1: ASD AD0-AD7 (read) CS AD0-AD7 (write) A8 & ASH t ASED t CYC t RWS t t DDR ASL t AHL ASL t AHL www.DataSheet4U.com 113 of 124 DS26502 T1/E1/J1/64KCC BITS Element RWH t DHR DSW t DHW ...
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... Nonmultiplexed Bus Table 20-2. AC Characteristics, Non-Mux Parallel Port = 3.3V ±5 0°C to +70°C for DS26502L DS26502LN.) PARAMETER Setup Time for A0 to A7, Valid to CS Active Setup Time for CS Active to Either RD, WR Active Delay Time from Either Active to Data Valid Hold Time from Either RD, WR, ...
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... 0ns min WR Address Valid Data Valid 5ns min/20ns max 0ns min t2 t3 75ns max Address Valid www.DataSheet4U.com t1 0ns min t2 t6 75ns min 115 of 124 DS26502 T1/E1/J1/64KCC BITS Element t5 t4 0ns min t7 t8 10ns 10ns min min t4 0ns min ...
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... 0ns min. DS Address Valid 5ns min. / 20ns max. t1 0ns min 75ns max. www.DataSheet4U.com Address Valid 10ns min. t1 0ns min 75ns min. 116 of 124 DS26502 T1/E1/J1/64KCC BITS Element Data Valid t5 t4 0ns min. 10ns t7 t8 min. t4 0ns min. ...
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... Serial Bus Table 20-3. AC Characteristics, Serial Bus = 3.3V ±5 0°C to +70°C for DS26502L DS26502LN.) CHARACTERISTIC DIAGRAM Operating Frequency (1) NUMBER Slave 1 Cycle Time: Slave 2 Enable Lead Time 3 Enable Lag Time Clock (CLK) High Time 4 Slave Clock (CLK) Low Time 5 Slave Data Setup Time (inputs) ...
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... INPUT NOTE: NOT DEFINED, BUT USUALLY LSB OF CHARACTER PREVIOUSLY TRANSMITTED BITS 6 MSB BITS 6-1 www.DataSheet4U.com SLAVE MSB MSB 118 of 124 DS26502 T1/E1/J1/64KCC BITS Element 3 SLAVE LSB NOTE 11 11 LSB 3 9 BITS 6-1 SLAVE LSB 11 LSB BITS 6-1 9 ...
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... Receive Side AC Characteristics Table 20-4. Receive Side AC Characteristics = 3.3V ±5 0°C to +70°C for DS26502L DS26502LN.) PARAMETER RCLK Period RCLK Pulse Width RCLK Pulse Width RCLK to RSER Delay RCLK to RS_8K, 400Hz Delay Note 1: E1 mode mode. Note 2: Note 3: Jitter attenuator enabled in the receive path. ...
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... RCLK t D1 RSER RS_8K 1 RS_8K 2 400HZ 3 NOTES: 1) RS_8K OUTPUT MODE. 2) RS_8K OUTPUT IN 64KCC MODE. 3) 400Hz OUTPUT ACTIVE ONLY IN 64KCC MODE, HIGH IMPEDANCE IN ALL OTHER MODES. DS26502 T1/E1/J1/64KCC BITS Element MSB of Channel F-Bit www.DataSheet4U.com 120 of 124 ...
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... TS_8K_4 in input mode. Note 5: TX CLOCK is an internal signal. Note 6: Note 7: TS_8K_4 in output mode. Note 8: TX CLOCK is an internal signal that samples TSER and TS_8K_4 when TS_8K_4 is in input mode. DS26502 T1/E1/J1/64KCC BITS Element SYMBOL MIN TYP 488 648 t CP 15.6 158.4 ...
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... NOTE 4: RCLK (THE RECOVERED LINE CLOCK) AND JA CLOCK (AN INTERNAL CLOCK DERIVED FROM MCLK) MAY BE SELECTED AS THE SOURCE FOR THE TRANSMIT PLL OR USED UNCONVERTED FOR TX CLOCK www.DataSheet4U.com Figure 3-3.) 122 of 124 DS26502 T1/E1/J1/64KCC BITS Element ...
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... New product release. Updated Table 2-1 and Table 2-2. Updated Figure 3-1. 032405 Replaced the older recommended LIU circuits in Section 13.8 with newer versions (Figure 13-4 and Figure 13-5, Table 13-1 and Table 13-2) Added timing information to Table 20-4 and updated Figure 20-11. DS26502 T1/E1/J1/64KCC BITS Element DESCRIPTION www.DataSheet4U.com 123 of 124 ...
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... are registered trademarks of Maxim Integrated Products, Inc., and Dallas Semiconductor Corporation. www.DataSheet4U.com 124 of 124 © 2005 Maxim Integrated Products · Printed USA DS26502 T1/E1/J1/64KCC BITS Element ...