K20P104M100SF2 Freescale Semiconductor, K20P104M100SF2 Datasheet - Page 39

• Manufacturer Part Number: K20P104M100SF2
• Description: K20 Sub-Family
• Manufacturer: Freescale Semiconductor

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4. The analog source resistance (R
5. The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs
6.6.1.4 16-bit ADC with PGA characteristics
Freescale Semiconductor, Inc.
dG/dV
dV
I
Symbol
DDA_PGA
CMRR
PSRR
dG/dT
in PGA gain without affecting other performances. This is not dependent on ADC clock frequency.
time should be allowed for F
8 MHz ADC clock. The ADLSTS bits can be adjusted for different ADC clock frequency
T
V
I
OFS
BW
G
LKG
GSW
OFS
G
A
/dT
DDA
Supply current
Leakage current
Gain
Gain error
Input signal band‐
width
Power supply re‐
jection ration
Common mode
rejection ratio
Input offset volt‐
age
Gain switching
settling time
Gain drift over
temperature
Offset drift over
temperature
Gain drift over
supply voltage
Description
2
Table 26. 16-bit ADC with PGA characteristics
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
in
=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at
PGA disabled
Gain=1
Gain=1
Conditions
AS
• PGAG=0
• PGAG=1
• PGAG=2
• PGAG=3
• PGAG=4
• PGAG=5
• PGAG=6
• 16-bit modes
• < 16-bit modes
• Gain=1
• Gain=64
• Gain=1
• Gain=64
• Gain=1
• Gain=64
), external to MCU, should be kept as minimum as possible. Increased R
Table continues on the next page...
Preliminary
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Min.
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Peripheral operating requirements and behaviors
Typ.
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29.9
590
< 1
3.9
0.2
—
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—
1
2
1
Max.
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±0.5
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40
10
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4
ppm/°C
ppm/°C
ppm/°C
Unit
kHz
kHz
%/V
%/V
mV
μA
μA
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
µs
0 to 50°C, ADC
V
Averaging=32
Averaging=32
AS
Gain=1, ADC
f
R
R
f
DDA
VDDA
VCM
500mVpp,
V
0 to 50°C
±100mV,
AS
AS
causes drop
to 3.6V
DDA
100Hz
Notes
V
60Hz
from 1.71
= 50Hz,
< 100Ω
< 100Ω
= 50Hz,
CM
3
= 3V
=
39
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