K20P104M100SF2 Freescale Semiconductor, K20P104M100SF2 Datasheet - Page 30

• Manufacturer Part Number: K20P104M100SF2
• Description: K20 Sub-Family
• Manufacturer: Freescale Semiconductor

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Peripheral operating requirements and behaviors
6.4.2 EzPort Switching Specifications
6.4.3 Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
30
EP1a
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
Num
EP1
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
Operating voltage
EZP_CK frequency of operation (all commands except
READ)
EZP_CK frequency of operation (READ command)
EZP_CS negation to next EZP_CS assertion
EZP_CS input valid to EZP_CK high (setup)
EZP_CK high to EZP_CS input invalid (hold)
EZP_D input valid to EZP_CK high (setup)
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid (setup)
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
Description
K20 Sub-Family Data Sheet Data Sheet, Rev. 1, 11/2010.
Table 21. EzPort switching specifications
EP3
EP5
Figure 9. EzPort Timing Diagram
EP6
EP4
EP7
Preliminary
EP8
EP9
EP2
2 x t
Min.
2.7
—
—
EZP_CK
—
—
5
5
2
5
0
Freescale Semiconductor, Inc.
f
f
Max.
SYS
SYS
3.6
12
12
—
—
—
—
—
—
/2
/8
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
V
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