TDA8752AH Philips Semiconductors, TDA8752AH Datasheet - Page 19

• Manufacturer Part Number: TDA8752AH
• Description: Triple high-speed Analog-to-Digital Converter ADC
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Table 5 Charge-pump current control
The default programmed value is as follows:
VCO
The bits Z2, Z1 and Z0 enable the internal resistance for
the VCO filter to be selected.
Table 6 VCO register bits
1999 Feb 24
Charge pump current = 100 A
Test bits: no test mode; bits Up and Do at logic 0
Rising edge of CKREF: bit edge at logic 0
COAST and HSYNC inputs are active HIGH: V level and
H level at logic 0.
Triple high-speed Analog-to-Digital
Converter (ADC)
Z2
Ip2
REGISTER
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Z1
0
0
1
1
0
0
1
1
Ip1
0
0
1
1
0
0
1
1
Z0
0
1
0
1
0
1
0
1
Ip0
0
1
0
1
0
1
0
1
high impedance
RESISTANCE
CURRENT
(k )
128
32
16
8
4
2
1
( A)
6.25
12.5
100
200
400
700
25
50
19
Table 7 VCO gain control
The bits V
The default programmed value is as follows:
D
This register controls the PLL frequency. The bits are the
LSB bits.
The default programmed value is 0011 0010 0000 = 800.
The MSB bits (Di11, Di10 and Di9) and the LSB bit (Di0)
have to be programmed before the bits Di8 to Di1 to have
the required divider ratio. The bit Di0 is used for the parity
divider number = Di0 = 0 = even number Di0 = 1 = odd
number. It should be noted that if the I
is done in mode = 1 and the bit Di0 has to be toggled, then
the registers have to be loaded twice to have the update
divider ratio.
P
PHASEA
The bit Cka is logic 0 when the used clock is the PLL clock,
and logic 1 when the used clock is the external clock.
The bit Ckb is logic 0 when the second clock is not used.
The bits Pa4 to Pa0 and Pb4 to Pb0 are used to program
the phase shift for the clock, CKADCO, CKAO and CKBO
(see Table 8).
OWER
IVIDER REGISTER
Internal resistance = 16 k
VCO gain = 15 MHz/V.
When the supply is completely switched off, the
registers are set to their default values; in that event they
have to be reprogrammed if the required settings are
different (e.g. through an EEPROM)
When the device is in power-down mode, the previously
programmed register values remain unaffected.
V
CO1
1
0
1
1
-
DOWN MODE
AND
CO1
and V
PHASEB
V
CO0
0
1
0
1
CO0
REGISTERS
control the VCO gain.
VCO gain
(MHz/V)
100
60
30
60
2
Product specification
C-bus programming
TDA8752A
PIXEL CLOCK
RANGE (MHz)
FREQUENCY
60 to 100
10 to 17
17 to 35
35 to 60