TDA8752AH Philips Semiconductors, TDA8752AH Datasheet - Page 18

• Manufacturer Part Number: TDA8752AH
• Description: Triple high-speed Analog-to-Digital Converter ADC
• Manufacturer: Philips Semiconductors

Philips Semiconductors
O
This register controls the clamp level for the
RGB channels. The relationship between the
programming code and the level of the clamp code is given
in Table 2.
Table 2 Coding
The default programmed value is:
C
These two registers enable the gain control, the AGC gain
with the coarse register and the reference voltage with the
fine register. The coarse register programming equation is
as follows:
Where: V
The gain correspondence is given in Table 3. The gain is
linear with reference to the programming code (N
1999 Feb 24
GAIN
PROGRAMMED
=
OARSE AND FINE REGISTERS
FFSET REGISTER
Programmed code = 127
Clamp code = 0
ADC output = 0.
Triple high-speed Analog-to-Digital
Converter (ADC)
------------------------------------------------ -
V
ref
CODE
N
=
127
254
255
COARSE
0
1
2
512 N
ref
--------------------------------------------- -
V
ref
= 2.5 V.
N
–
COARSE
1
+
FINE
–
1
------------------ -
32 16
N
CLAMP CODE
FINE
+
1
32
63.5
63.5
62.5
64
63
0
----- -
16
1
ADC OUTPUT
underflow
63 or 64
64
0
FINE
= 0).
18
Table 3 Gain correspondence (COARSE)
The default programmed value is as follows:
To modulate this gain, the fine register is programmed
using the above equation. With a full-scale ADC input, the
fine register resolution is a
(see Table 4 for N
Table 4 Gain correspondence (FINE)
The default programmed value is: N
C
COAST and HSYNC signals can be inverted by setting the
I
V level and H level are set to zero respectively, COAST
and HSYNC are active HIGH.
The bit ‘edge’ defines the rising or falling edge of CKREF
to synchronise the PLL. It will be on the rising edge if the
bit is at logic 0 and on the falling edge if the bit is at logic 1.
The bits Up and Do are used for the test, to force the
charge pump current. These bits have to be logic 0 during
normal use.
The bits Ip0, Ip1 and Ip2 control the charge pump current,
to increase the bandwidth of the PLL, as shown in Table 5.
2
C-bus control bits V level and H level respectively. When
ONTROL REGISTER
N
Gain = 0.825
V
i
COARSE
to be full-scale = 1.212.
N
COARSE
N
32
99
31
FINE
0
= 32
COARSE
= 32).
GAIN
0.825
GAIN
0.825
0.878
1
2.5
2
LSB peak-to-peak
FINE
Product specification
TDA8752A
= 0.
FULL-SCALE
FULL-SCALE
V
V
i
i
1.212
1.212
1.139
TO BE
TO BE
0.4