ISL6123 Intersil Corporation, ISL6123 Datasheet - Page 7

• Manufacturer Part Number: ISL6123
• Description: Power Sequencing Controllers
• Manufacturer: Intersil Corporation

Typical Performance Curves
Using the ISL612XSEQEVAL1 Platform
The ISL612XSEQEVAL1 platform is the primary evaluation
board for this family. The board has 2 complete, separate
and electrically identical circuits, see Figure 11 for schematic
and Figure 12 for a photo.
In the top right hand corner of the board is a SMD layout with
a ISL6123 illustrating the full functionality and small
implementation size for an application having the highest
component count.
The majority of the board is given over to a socket and
discrete through-hole components circuit for ease of
evaluation flexibility through IC variant swapping and
modification of UVLO levels and sequencing order by
passive component substitution.
The board is shipped with the ISL6123 installed in both
locations and with two each of the other released variant
types loose packed. As this sequencer family has a common
function pinout there are no major modifications to the board
necessary to evaluate the other ICs. The ISL6125 due to its
having open drain outputs can be evaluated on the
ISL612XSEQEVAL1 with a minor modification or on the
ISL613XSUPEREVAL2 evaluation platform. To modify for
ISL6125 evaluation, pull-up resistors must be added from
the GATE outputs to a pull-up voltage of 1.5V to prevent
FET turn-on or remove FETs to eliminate this voltage
restriction.
To the left, right and above the socket are four test point
strips (TP1-TP4). These give access to the labeled IC I/O
pins during evaluation. Remember that significant current or
capacitive loading of particular I/O pins will affect
functionality and performance.
7
FIGURE 6. SYSRST# LOW TO OUTPUT LATCH OFF
2V/DIV
SYSRST#
(Continued)
ISL6123, ISL6124, ISL6125
3.3VOUT
5VOUT
GATE
Attention to orientation and placement of variant ICs in the
socket must be paid to prevent IC damage or faulty
evaluation.
The default configuration of the ISL612XSEQEVAL1
circuitries was built around the following design
presumptions:
Figures 7 and 8 illustrate the desired turn-on and turn-off
sequences respectively. The sequencing order and delay
between voltages sequencing is set by external capacitance
values so other than illustrated can be accomplished.
Figures 9 and 10 illustrate the timing relationships between
the EN input, RESET#, DLY and GATE outputs and the
VOUT voltage for a single channel being turned on and off
respectively. RESET# is not shown in Figure 9 as it asserts
160ms after the last GATE goes high.
1. Using the ISL6123IR or ISL6124IR
2. The four supplies being sequenced are 5V (IN_A), 3.3V
3. The desired order turn-on sequence is first both 5V and
4. The desired turn-off sequence is first both 1.5V and 3.3V
(IN_B), 2.5V (IN_C) and 1.5V (IN_D), the UVLO levels
are ~ 80% of nominal voltages. Resistors chosen such
that the total resistance of each divider is ~ 10K using
standard value resistors to approximate 80% of nominal
= 0.63V on UVLO input.
3.3V supplies together and then the 2.5V supply about
75ms later and lastly the 1.5V supply about 45ms later.
supplies at the same time then the 2.5V supply about
50ms later and lastly the 5V supply about 72ms after that.
1µs/DIV