ISL6123 Intersil Corporation, ISL6123 Datasheet - Page 4

• Manufacturer Part Number: ISL6123
• Description: Power Sequencing Controllers
• Manufacturer: Intersil Corporation

Electrical Specifications
ISL6123, ISL6124, ISL6125 Descriptions and Operation
The ISL6123, ISL6124, ISL6125 sequencer family consists
of several four channel voltage sequencing controllers in
various functional and personality configurations. All are
designed for use in multiple-voltage systems requiring
power sequencing of various supply voltages. Individual
voltage rails are gated on and off by external N-Channel
MOSFETs, the gates of which are driven by an internal
charge pump to V
sequence.
With the four-channel ISL6123 the ENABLE must be
asserted and all four voltages to be sequenced must be
above their respective user programmed Under Voltage
Lock Out (UVLO) levels before programmed output turn on
sequencing can begin. Sequencing and delay
determination is accomplished by the choice of external
cap values on the DLY_ON and DLY_OFF pins. Once all 4
UVLO inputs and ENABLE are satisfied for ~ 9ms, the four
DLY_ON caps are simultaneously charged with 1µA
current sources to the DLY_Vth level of ~ 1.27V. As each
DLY_ON pin reaches the DLY_Vth level its associated
GATE will then turn-on with a 1µA source current to the
VQP voltage of V
sequentially turn on. Once at DLY_Vth the DLY_ON pins
will discharge to be ready when next needed. After the
entire turn on sequence has been completed and all
GATEs have reached the charge pumped voltage (VQP), a
160ms delay is started to ensure stability after which the
RESET# output will be released to go high. Subsequent to
turn-on, if any input falls below its UVLO point for longer
than the glitch filter period (~ 30µs) this is considered a
fault. RESET# is asserted low and all GATEs are
simultaneously pulled low. In this mode the GATEs are
pulled low with 88mA. Normal shutdown mode is entered
when no UVLO is violated and the ENABLE is deasserted.
When ENABLE is deasserted, RESET# is asserted and
pulled low. Next, all four shutdown ramp caps on the
DLY_OFF pins are charged with a 1µA source and when
any ramp-cap reaches DLY_Vth, a latch is set and a
current is sunk on the respective GATE pin to turn off its
external MOSFET. When the GATE voltage is
approximately 0.6V, the GATE is pulled down the rest of
the way at a higher current level. Each individual external
FET is thus turned off removing the voltages from the load
in the programmed sequence.
BIAS
IC Supply Current
IC Supply Current
IC Supply Current
ISL6123 Stand By IC Supply Current
V
DD
Power On Reset
PARAMETER
DD
DD
+5V. Thus all four GATEs will
+5V (VQP) in a user programmed
4
V
DD
= 1.5V to +5V, T
V
I
I
SYMBOL
VDD_3.3V
VDD_1.5V
I
I
DD
VDD_5V
VDD_sb
ISL6123, ISL6124, ISL6125
_POR
A
= T
J
V
V
V
V
= -40
DD
DD
DD
DD
= 5V
= 3.3V
= 1.5V
= 5V, ENABLE = 0V
o
TEST CONDITIONS
C - 85
o
The ISL6123 and ISL6124 have the same functionality
except for the ENABLE active polarity with the ISL6124
having an ENABLE# input. Additionally the ISL6123 also
has an ultra low power sleep state when ENABLE is low.
The ISL6125 has the same personality as the ISL6124 but
instead of charged pump driven GATE outputs it has open
drain LOGIC outputs that can be pulled up to a maximum of
V
During bias up the RESET# output is guaranteed to be in
the correct state with V
The SYSRST# input once asserted low unconditionally
shuts off all GATEs, see Figure 6. This input can be used
as a no wait enabling input, if all inputs (ENABLE & UVLO)
are satisfied. It is also useful when multiple sequencers are
implemented in a design needing simultaneous shutdown
(kill switch) across all sequencers.
After a fault, restart of the turn on sequence is automatic
once all requirements are met. This allows for no
interaction between the sequencer and a controller IC if
desired. The ENABLE & RESET# I/O do allow for a higher
level of feedback and control if desired.
If no capacitors are connected between DLY_ON or
DLY_OFF pins and ground then all such related GATEs
start to turn on immediately after the ~ 9ms(T
ENABLE stabilization time out has expired and the GATEs
start to immediately turn off when ENABLE is asserted.
Table 1 illustrates the nominal time delay from the start of
charging to the 1.24V reference for various capacitor
values on the DLY_ON and DLY_OFF pins. This table does
not include the ~ 9ms of enable lock out delay during a
start up sequence but represents the time from the end of
the enable lock out delay to the start of GATE transition.
There is no enable lock out delay for a sequence off, so this
table illustrates the delay to GATE transition from a disable
signal. Bold fields in table illustrate most likely used range
of delay periods.
C, Unless Otherwise Specified. (Continued)
DD
.
MIN
DD
lower than 1V.
TYP
0.20
0.14
0.10
100
MAX
0.5
1
UVLOdel
UNIT
mA
mA
mA
)
µA
V