ISL6123 Intersil Corporation, ISL6123 Datasheet - Page 2

• Manufacturer Part Number: ISL6123
• Description: Power Sequencing Controllers
• Manufacturer: Intersil Corporation

Pinout
Pin Descriptions
PIN NUMBER
9, 11, 19
23
10
24
20
12
17
14
21
16
15
18
13
22
1
8
3
4
2
5
6
7
ISL6123/24 ISL6125
GATE_A LOGIC_A
GATE_B LOGIC_B
GATE_C LOGIC_C
GATE_D LOGIC_D
DLY_OFF_C
DLY_OFF_D
DLY_OFF_A
DLY_OFF_B
DLY_ON_A
DLY_ON_B
DLY_ON_C
DLY_ON_D
No Connect
PIN NAME
ENABLE#
SYSRST#
ENABLE/
RESET#
UVLO_A
UVLO_B
UVLO_C
UVLO_D
GND
V
DD
2
Chip Bias
Bias Return
Starts on/off
sequencing of the
power supplies.
Reset Output
Under Voltage Lock
Out/Monitoring
Gate On Delay
Timer Capacitor
Gate Off Delay
Timer Capacitor
FET Gate Drive
Output
ISL6125 Open
Drain Outputs
System Reset
No Connect
FUNCTION
ISL6123, ISL6124, ISL6125 (24 LEAD QFN)
ISL6123, ISL6124, ISL6125
1
2
3
4
5
6
24
7
Bias IC from 1.5V to 5.5V
IC ground
Input to initiate the start of the programmed sequencing of supplies on or off.
ISL6123 has ENABLE. ISL6124, ISL6125 have ENABLE#.
RESET# provides a high signal ~160ms after all GATEs are fully enhanced. This
delay is for stabilization of output voltages. RESET# will assert upon UVLO not being
satisfied or ENABLE / ENABLE# being deasserted.
The RESET# output is an open drain N channel FET and is guaranteed to be in the
correct state for V
These inputs provide for a programmable UV lockout referenced to an internal
0.633V reference and are filtered to ignore short (~ 30µs) transients below programmed
UVLO level.
Allows for programming the delay and sequence for VOUT turn-on. Each cap is
charged with 1µA ~9ms after ENABLE / ENABLE# with an internal current source
providing delay to the associated FETs turn-on.
Allows for programming the sequence for Vout turn-off through ENABLE / ENABLE#.
Each cap is charged with a 1µA internal current source to an internal reference
voltage causing the corresponding gate to be pulled down turning-off the associated
FET.
Drives the external FETs with a 1µA current source to soft start ramp into the load.
On the ISL6125 only these are open drain inputs that can be pulled up to a maximum
of V
Allows for immediate unconditional latch-off of all GATE outputs when driven low.
This input can also be used to initiate the programmed sequence with ‘zero’ wait (no
9ms stabilization delay) from input signal on this pin being driven high to first GATE.
No Connect
23
8
4mm x 4mm
DD
TOP VIEW
22
9
voltage.
21
10
11
DD
20
< 1V.
12
19
18
17
16
15
14
13
DESCRIPTION