GS1559 Gennum Corp., GS1559 Datasheet - Page 63

• Manufacturer Part Number: GS1559
• Description: GS1559 HD-LINX-TM II Multi-Rate Deserializer with Loop-Through Cable Driver
• Manufacturer: Gennum Corp.

4.11.5 Parallel Output Clock (PCLK)
Table 4-16: Parallel Data Output Format
Output Data Format
SMPTE MODE
20bit DEMULTIPLEXED SD
10bit MULTIPLEXED SD
20bit DEMULTIPLEXED HD
10bit MULTIPLEXED HD
DVB-ASI MODE
10bit DVB-ASI
DATA-THROUGH MODE**
20bit DEMULTIPLEXED SD
10bit MULTIPLEXED SD
20bit DEMULTIPLEXED HD
10bit MULTIPLEXED HD
*NOTE1: Recall that SD/HD, SMPTE_BYPASS, and DVB_ASI are input control pins in slave mode to be set by the application layer, but are
output status signals set by the device in master mode.
**NOTE 2: Data-Through mode is only available in slave mode
DOUT
[19:10]
LUMA
LUMA /
CHROMA
LUMA
LUMA /
CHROMA
DVB-ASI
DATA
DVB-ASI
DATA
DATA
DATA
DATA
DATA
As described in
forced to logic LOW if the device is set to operate in master mode but cannot
identify SMPTE TRS ID or DVB-ASI sync words in the input data stream.
The frequency of the PCLK output signal of the GS1559 is determined by the
output data format.
their corresponding parallel clock rates. Note that DVB-ASI output will always be in
10-bit format, regardless of the setting of the 20bit/10bit pin.
30572 - 4
DOUT
[9:0]
CHROMA
FORCED
LOW
CHROMA
FORCED
LOW
FORCED
LOW
FORCED
LOW
DATA
FORCED
LOW
DATA
FORCED
LOW
July 2005
Data Through Mode on page
PCLK
27MHz
74.25 or
74.25/
1.001MHz
148.5 or
148.5/
1.001MHz
27MHz
27MHz
27MHz
74.25 or
74.25/
1.001MHz
148.5 or
148.5/
1.001MHz
13.5MHz
13.5MHz
Data Through Mode on page
Table 4-16
20bit/
10bit
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
below lists the possible output signal formats and
SD/HD
HIGH
HIGH
LOW
LOW
HIGH
HIGH
HIGH
HIGH
LOW
LOW
Status / Control Signals*
42.
42, the data bus outputs will be
SMPTE_BYPASS
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
GS1559 Data Sheet
DVB_ASI
LOW
LOW
LOW
LOW
HIGH
HIGH
LOW
LOW
LOW
LOW
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