RTL8169S-32 ETC-unknow, RTL8169S-32 Datasheet - Page 19

• Manufacturer Part Number: RTL8169S-32
• Description: Single-chip Gigabit Nic Ethernet Controller
• Manufacturer: ETC-unknow

RTL8169S-32/RTL8169S-64
Datasheet
6.2. MAC
The RTL8169S supports new descriptor-based buffer management that significantly reduces host CPU
utilization and is particularly effective in server applications. The new buffer management algorithm
provides Microsoft Large-Send offload, IP checksum offload, TCP checksum offload, UDP checksum
offload, and IEEE 802.1P, 802.1Q VLAN tagging capabilities. The device supports up to 1024
consecutive descriptors in memory for transmit and receive separately, which means there might be 3
descriptor rings, one a high priority transmit descriptor ring, another a normal priority transmit descriptor
ring, and the other a receive descriptor ring. Each descriptor ring may consist of up to 1024 consecutive
descriptors. Each descriptor consists of 4 consecutive double words. The start address of each descriptor
ring should be 256-byte aligned. Software must pre-allocate enough buffers and configure all descriptor
rings before transmitting and/or receiving packets. Descriptors can be chained to form a packet in both Tx
and Rx. Refer to the Realtek RTL8169S Programming Guide for detailed information. Any Tx buffers
pointed to by the Tx descriptors should be at least 4 bytes.
The RTL8169S will automatically pad any packets less than 64 bytes to 64-bytes long (including a 4-byte
CRC) before transmitting that packet onto the network medium. If a packet consists of two or more
descriptors, then the descriptors in command mode should have the same configuration, except EOR, FS,
LS bits.
6.3. Next Page
If 1000Base-T mode is advertised, three additional Next Pages are automatically exchanged between the
two link partners. Users can set Reg4.15 to 1 to exchange extra Next Pages via Reg7 and Reg8 as defined
in IEEE 802.3ab.
Integrated Gigabit Ethernet Controller (NIC)
13
Track ID: JATR-1076-21
Rev. 1.7