BS2824 Holtek Semiconductor Inc., BS2824 Datasheet - Page 40

• Manufacturer Part Number: BS2824
• Description: Touch Key Mcu
• Manufacturer: Holtek Semiconductor Inc.

BS2824/BS2854/BS2868
Touch Key MCU
Rev. 1.00
WDTS Register
f
that operate in noisy environments, using the LIRC or the LXT as the clock source is therefore the
recommended choice. The division ratio of the prescaler is determined by bits 0, 1 and 2 of the WDTS
register, known as WS0, WS1 and WS2. If the Watchdog Timer internal clock source is selected and
with the WS0, WS1 and WS2 bits of the WDTS register all set high, the prescaler division ratio will be
1:128, which will give a maximum time-out period.
Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set
the status bit TO. However, if the system is in the Idle/Sleep Mode, when a Watchdog Timer
time-out occurs, the device will be woken up, the TO bit in the status register will be set and only the
Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents
of the Watchdog Timer. The first is an external hardware reset, which means a low level on the
external reset pin, the second is using the Clear Watchdog Timer software instructions and the third
is when a HALT instruction is executed. There are two methods of using software instructions to
clear the Watchdog Timer, one of which must be chosen by configuration option. The first option is
to use the single CLR WDT instruction while the second is to use the two commands CLR
WDT1 and CLR WDT2 . For the first option, a simple execution of CLR WDT will clear the
Watchdog Timer while for the second option, both CLR WDT1 and CLR WDT2 must both be
executed to successfully clear the Watchdog Timer. Note that for this second option, if CLR
WDT1 is used to clear the Watchdog Timer, successive executions of this instruction will have no
effect, only the execution of a CLR WDT2 instruction will clear the Watchdog Timer. Similarly
after the CLR WDT2 instruction has been executed, only a successive CLR WDT1 instruction
can clear the Watchdog Timer.
SYS
Bit 7~3 : unimplemented, read as 0
Bit 2~0
Name
POR
R/W
/4 as the Watchdog Timer clock source, the Watchdog Timer will cease to function. For systems
Bit
WS2, WS1, WS0: WDT time-out period selection
000: 2
001: 2
010: 2
011: 2
100: 2
101: 2
110: 2
111: 2
7
15
11
14
8
9
10
12
13
t
t
WDTCK
WDTCK
t
t
t
t
t
t
WDTCK
WDTCK
WDTCK
WDTCK
WDTCK
WDTCK
6
5
40
Watchdog Timer
4
3
WS2
R/W
2
1
WS1
R/W
1
1
January 27, 2010
WS0
R/W
0
1