PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 434

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0800H: PRGM Indirect Address
Register 0810H: PRGM Aux 2 Indirect Address
Register 0820H: PRGM Aux 3 Indirect Address
Register 0830H: PRGM Aux 4 Indirect Address
PATH[3:0]
IADDR[3:0]
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The STS-1/STM-0 path (PATH[3:0]) bits select which STS-1/STM-0 path is accessed by the
current indirect transfer. For the S/UNI-2488, PATH[3:0] is normally set to 1H except when
accessing the monitor error counter registers.
The internal address bits select which internal register is accessed by the current indirect
transfer. Six registers are defined for the monitor while four pages are defined for the
generator.
IADDR[3:0]
0000
0001
0010
0011
0100
0101
1000
1001
R
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BUSY
RWB
Unused
Unused
Unused
Unused
IADDR[3]
IADDR[2]
IADDR[1]
IADDR[0]
PATH[3]
PATH[2]
PATH[1]
PATH[0]
Function
Unused
Unused
Register
Monitor – Timeslot Configuration page
Monitor – PRBS[22:7] page
Monitor – PRBS[6:0] page
Reserved
Monitor – Monitor error count page
Reserved
Generator – Timeslot Configuration page
Generator – PRBS[22:7] page
S/UNI-2488 Telecom Standard Product Datasheet
Default
X
0
X
X
X
X
0
0
0
0
X
X
0
0
0
0
Released
434