PM5381-BI PMC-Sierra, Inc., PM5381-BI Datasheet - Page 359

• Manufacturer Part Number: PM5381-BI
• Description: ATM UNI, Single Channel ATM PHY Interface for 2488.32Mbps
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2000489, Issue 4
Register 0740H: RCFP Configuration
All Reserved bits must be set to their default values for proper operation.
PROV
DESCRMBL
RXOTYP
Bit
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The processor provision bit (PROV) is used to enable the RCFP. When PROV is logic 0, the
RCFP ATM and packet processors are disabled and will not transfer any valid data to the
Receive FIFO interface. When PROV is logic 1, the RCFP ATM or packet processor is
enabled and will process data presented to it and transfer data to the Receive FIFO (RXSDQ).
The DESCRMBL bit controls the descrambling of the packet or ATM cell payload with the
polynomial x
is disabled. When DESCRMBL is set to logic 1, payload descrambling is enabled.
The RXOTYP bit determines if an incoming alarm signal (from IPAIS[x]) will stop a packet
by simply asserting EOP, (RXOTYP set to logic 0), or by asserting both EOP and ERR,
(RXOTYP set to logic 1). When RXOTYP is set to logic 0, premature termination of the
packet will result in that packet failing a FCS check.
This bit is only valid when in POS mode. In ATM mode the RCFP will finish processing any
cell in progress and then stop until the alarm signal is cleared.
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
43
+ 1. When DESCRMBL is set to logic 0, frame or cell payload descrambling
Function
Reserved
Reserved
Reserved
Reserved
Reserved
POS_SEL
INVERT
STRIP_SEL
DELINDIS
IDLEPASS
CRCPASS
CRC_SEL[1]
CRC_SEL[0]
RXOTYP
DESCRMBL
PROV
S/UNI-2488 Telecom Standard Product Datasheet
Default
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
Released
359