MSC7119 Freescale Semiconductor / Motorola, MSC7119 Datasheet - Page 48

• Manufacturer Part Number: MSC7119
• Description: Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC
• Manufacturer: Freescale Semiconductor / Motorola

Hardware Design Considerations
When booting from a power-on reset, the HDI16 is additionally configurable as follows:
These pins are sampled only on the deassertion of power-on reset. During a boot from a hard reset, the configuration of these
pins is unaffected.
Note:
3.4.3.2
When the MSC7119 device is configured to boot from the I
operation. Then the MSC7118 device initiates accesses to the I
interface is configured as follows:
The IPBus clock is internally divided to generate the bit clock, as follows:
This satisfies the maximum clock rate requirement of 400 kbps for the I
“Boot Program” chapter of the MSC711x Reference Manual.
3.4.3.3
When the MSC7119 device is configured to boot from the SPI port, the boot program configures the GPIO pins for SPI
operation. Then the MSC7118 device initiates accesses to the SPI module, downloading data to the MSC7118 device. When
the SPI routines run in the boot ROM, the MSC7118 is always configured as the SPI master. Booting through the SPI is
supported for serial EEPROM devices and serial Flash devices. When a READ_ID instruction is issued to the serial memory
device and the device returns a value of 0x00 or 0xFF, the routines for accessing a serial EEPROM are used, at a maximum
frequency of 4 Mbps. Otherwise, the routines for accessing a serial Flash are used, and they can run at faster speeds. Booting is
performed through one of two sets of pins:
In either configuration, an error during SPI boot is flagged on the EVNT3 pin. For details on the boot procedure, see the “Boot
Program” chapter of the MSC711x Reference Manual.
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8- or 16-bit mode as specified by the
Data strobe as specified by the
When the HDI16 is used for booting or other purposes, bit 0 is the least significant bit and not the most significant bit
as for other DSP products.
PLL is disabled and bypassed so that the I
I
EPROM operates in slave mode.
Clock divider is set to 128.
Address of slave during boot is 0xA0.
CLKIN must be a maximum of 100 MHz
PLL is bypassed.
IPBus clock = CLKIN/2 is a maximum of 50 MHz.
I
— IPBus clock/I
— 50 MHz (max)/128
— 390.6 KHz
Main set: BM[2–3], HA3, and HCS2, which allow use of the PLL.
Alternate set: UTXD, URXD, SDA, and SCL, which cannot be used with the PLL.
2
2
C interface operates in master mode and polling is used.
C bit clock must be less than or equal to:
I
SPI Boot
2
C Boot
2
C clock divider
MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6
HDSP
H8BIT
and
2
HDDS
C module is clocked with the IPBus clock.
pin.
pins.
2
C port, the boot program configures the GPIO pins for I
2
C module, downloading data to the MSC7118 device. The I
2
C interface. For details on the boot procedure, see the
Freescale Semiconductor
2
C
2
C