MSC7119 Freescale Semiconductor / Motorola, MSC7119 Datasheet - Page 2

• Manufacturer Part Number: MSC7119
• Description: Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC
• Manufacturer: Freescale Semiconductor / Motorola

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List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
2
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1
1.2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.1
2.2
2.3
2.4
2.5
Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . .41
3.1
3.2
3.3
3.4
3.5
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
FC-PBGA Ball Layout Diagrams . . . . . . . . . . . . . . . . . . .4
Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .6
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Recommended Operating Conditions. . . . . . . . . . . . . .18
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .19
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .19
AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Thermal Design Considerations . . . . . . . . . . . . . . . . . .41
Power Supply Design Considerations. . . . . . . . . . . . . .42
Estimated Power Usage Calculations. . . . . . . . . . . . . .44
Reset and Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
DDR Memory System Guidelines . . . . . . . . . . . . . . . . .49
MSC7119 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . 3
MSC7119 Molded Array Process-Ball Grid Array
(MAP-BGA), Top View . . . . . . . . . . . . . . . . . . . . . . . . . 4
MSC7119 Molded Array Process-Ball Grid Array
(MAP-BGA), Bottom View . . . . . . . . . . . . . . . . . . . . . . 5
Timing Diagram for a Reset Configuration Write . . . . 25
DDR DRAM Input Timing Diagram . . . . . . . . . . . . . . 26
MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6
Table of Contents
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10. Ethernet Receive Signal Timing . . . . . . . . . . . . . . . . . 29
Figure 11. Ethernet Receive Signal Timing . . . . . . . . . . . . . . . . . 30
Figure 12. Asynchronous Input Signal Timing . . . . . . . . . . . . . . . 30
Figure 13. Serial Management Channel Timing . . . . . . . . . . . . . 31
Figure 14. Read Timing Diagram, Single Data Strobe . . . . . . . . 33
Figure 15. Read Timing Diagram, Double Data Strobe . . . . . . . . 33
Figure 16. Write Timing Diagram, Single Data Strobe. . . . . . . . . 34
Figure 17. Write Timing Diagram, Double Data Strobe . . . . . . . . 34
Figure 18. Host DMA Read Timing Diagram, HPCR[OAD] = 0 . . 35
Figure 19. Host DMA Write Timing Diagram, HPCR[OAD] = 0 . . 35
Figure 20. I2C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 21. UART Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 22. UART Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 23. EE Pin Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 24. EVNT Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 25. GPI/GPO Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 26. Test Clock Input Timing Diagram . . . . . . . . . . . . . . . . 39
Figure 27. Boundary Scan (JTAG) Timing Diagram . . . . . . . . . . 40
Figure 28. Test Access Port Timing Diagram . . . . . . . . . . . . . . . 40
Figure 29. TRST Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 30. Voltage Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 31. PLL Power Supply Filter Circuits . . . . . . . . . . . . . . . . 43
Figure 32. SSTL Termination Techniques . . . . . . . . . . . . . . . . . . 49
Figure 33. SSTL Power Value . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
DDR DRAM Output Timing Diagram . . . . . . . . . . . . . 27
DDR DRAM AC Test Load . . . . . . . . . . . . . . . . . . . . . 28
TDM Receive Signals. . . . . . . . . . . . . . . . . . . . . . . . . 28
TDM Transmit Signals . . . . . . . . . . . . . . . . . . . . . . . . 29
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