MSC7119 Freescale Semiconductor / Motorola, MSC7119 Datasheet - Page 43

• Manufacturer Part Number: MSC7119
• Description: Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC
• Manufacturer: Freescale Semiconductor / Motorola

Freescale Semiconductor
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Power planes. Each power supply pin (
supply. Each
groups of logic on the device. The MSC7119
capacitors. The capacitor leads and associated printed circuit traces connecting to device power pins and
be kept to less than half an inch per capacitor lead. A minimum four-layer board that employs two inner layers as power
and
Decoupling. Both the I/O voltage and core voltage should be decoupled for switching noise. For I/O decoupling, use
standard capacitor values of 0.01 μF for every two to three voltage pins. For core voltage decoupling, use two levels
of decoupling. The first level should consist of a 0.01 µF high frequency capacitor with low effective series resistance
(ESR) and effective series inductance (ESL) for every two to three voltage pins. The second decoupling level should
consist of two bulk/tantalum decoupling capacitors, one 10 μF and one 47 μF, (with low ESR and ESL) mounted as
closely as possible to the MSC7119 voltage pins. Additionally, the maximum drop between the power supply and the
DSP device should be 15 mV at 1 A.
PLL power supply filtering. The MSC7119
ensure stability of the internal clock, the power supplied to this pin should be filtered with capacitors that have low and
high frequency filtering characteristics.
directly to the
be placed as closely as possible to the
minimize noise coupled from nearby circuits.The 0.01 µF capacitor should be closest to
µF capacitor, the 10 µF capacitor, and finally the 20-Ω resistor to
GND
0.7 V or More
planes is recommended. See Section 3.5 for DDR Controller power guidelines.
GND
GND
pin should be provided with a low-impedance path to ground. The power supply pins drive distinct
plane. A circuit similar to the one shown in Figure 31 is recommended. The PLL loop filter should
Ramp-up
MSC7119 10/100 Mbps Ethernet MAC Data Sheet, Rev. 6
V
DDC
Figure 31. PLL Power Supply Filter Circuits
Figure 30. Voltage Sequencing
20
V
V
Ω
V
DDPLL
DDC
DDPLL
Differential should always be
0.7 V or more.
V
,
V
DDPLL
V
10 µF
pin (which are located on the outside edge of the silicon package) to
DDC
DDM,
can be connected to V
V
V
V
DDIO
power supply pins should be bypassed to ground using decoupling
DDM
DDC
power signal provides power to the clock generation PLL. To
and
Time
= 1.2 V
= 2.5 V
= 3.3 V
V
DDIO
0.1 µF 0.01 µF
) should have a low-impedance path to the board power
V
DDC
DDC
. These traces should be kept short.
through a 20 Ω resistor. V
V
DDPLL
Hardware Design Considerations
Ramp-down
V
0.7 V or More
DDPLL
, followed by the 0.1
SSPLL
GND
can be tied
should
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