STPCC4 STMicroelectronics, STPCC4 Datasheet - Page 82

• Manufacturer Part Number: STPCC4
• Description: STPC CONSUMER-II DATASHEET - X86 CORE PC COMPATIBLE INFORMATION APPLIANCE SYSTEM-ON-CHIP
• Manufacturer: STMicroelectronics

DESIGN GUIDELINES
6.4.4.3. Board Layout Issues
The physical layout of the motherboard PCB
assumed in this presentation is as shown inFigure
6-24. For the PCI interface, the most critical signal
is the clock. Any skew between the clocks at the
PCI components and the STPC will impact the
timing budget. In order to get well matched clocks
at all components it is recommended that all the
PCI clocks are individually driven from a serial
resistance with matched routing lengths. In other
The Figure 6-25 describes a typical clock delay
implementation. The exact timing constraints are
82/93
Note: The value of 22 Ohms corresponds to tracks with Z
HCLK
PCICLKO
PCICLKI
PCICLKx
PCICLKO
PCICLKI
Figure 6-24. Typical PCI clock routing
Figure 6-25. Clocks relationships
Release 1.5 - January 29, 2002
0
Length(PCICLKI) = Length(PCICLKx) with x = {A,B,C}
words, all clock line lengths that go from the
resistor to the PCI chips (PCICLKx) must be
identical.
The figure below is for PCI devices soldered on-
board. In the case of a PCI slot, the wire length
must be shortened by 2.5” to compensate the
clock layout on the PCI board. The maximum
clock skew between all devices is 2ns according
to PCI specifications.
listed in the PCI section of the Electrical
Specifications Chapter.
= 70 Ohms.
PCICLKA
PCICLKB
PCICLKC
Device A
Device B
Device C