STPCC4 STMicroelectronics, STPCC4 Datasheet - Page 3

• Manufacturer Part Number: STPCC4
• Description: STPC CONSUMER-II DATASHEET - X86 CORE PC COMPATIBLE INFORMATION APPLIANCE SYSTEM-ON-CHIP
• Manufacturer: STMicroelectronics

The STPC Consumer-II has undergone an errata fix upgrade. The different versions can be differenciated by the part
number. Both versions are pin to pin compatible and there are some software extensions that have been added to the
upgraded parts. The parts labeled STPCC5 are the upgraded parts and the differences are identified in both the Datash-
eet and Programming Manual. All parts labeled STPCC4 do not support the new features outlined in the documentation.
Where nor C4 nor C5 are specified, the information or feature applies to both versions.
PCI Controller
Fully compliant with PCI 2.1 specification.
Integrated PCI arbitration interface. Up to 3
Translation of PCI cycles to ISA bus.
Translation of ISA master initiated cycle to
Support for burst read/write from PCI master.
PCI clock is 1/2, 1/3 or 1/4 cpu bus clock.
ISA master/slave
Generates the ISA clock from either
Supports programmable extra wait state for
Supports I/O recovery time for back to back
Fast Gate A20 and Fast reset.
Supports the single ROM that C, D, or E.
Supports flash ROM.
Supports ISA hidden refresh.
Buffered DMA & ISA master cycles to reduce
Local Bus interface
Multiplexed with ISA/DMA interface.
Low latency asynchronous bus
22-bit address bus.
16-bit data bus with word steering capability.
Programmable timing (Host clock granularity)
Two Programmable Flash Chip Select.
Four Programmable I/O Chip Select.
Supports 32-bit Flash burst.
Two-level hardware key protection for Flash
Supports two banks of 16 MB flash devices
masters can connect directly. External PAL
allows for greater than 3 masters.
PCI.
14.318 MHz oscillator clock or PCI clock
ISA cycles
I/O cycles.
blocks shares with F block BIOS ROM.
bandwidth utilization of the PCI and Host
bus.
boot block protection.
with boot block shadowed to 0x000F0000.
Release 1.5 - January 29, 2002
IDE Interface
Supports PIO
Transfer Rates to 22 MBytes/sec
Supports up to 4 IDE devices
Concurrent channel operation (PIO modes) -
Support for PIO mode 3 & 4.
Individual drive timing for all four IDE devices
Supports both legacy & native IDE modes
Supports hard drives larger than 528MB
Support for CD-ROM and tape peripherals
Backward compatibility with IDE (ATA-1).
Drivers for Windows and other Operating
Integrated Peripheral Controller
2X8237/AT compatible 7-channel DMA
2X8259/AT compatible interrupt Controller.
Three 8254 compatible Timer/Counters.
Co-processor error support logic.
Power Management
Four power saving modes: On, Doze,
Programmable system activity detector
Supports Intel & Cyrix SMM and APM.
Supports STOPCLK.
Supports IO trap & restart.
Independent peripheral time-out timer to
128K SM_RAM address space from
JTAG
Boundary Scan compatible IEEE1149.1.
Scan Chain control.
Bypass register compatible IEEE1149.1.
ID register compatible IEEE1149.1.
RAM BIST control.
4 x 32-Bit Buffer FIFOs per channel
Systems
controller.
16 interrupt inputs - ISA and PCI.
Standby, Suspend.
monitor hard disk, serial & parallel port.
0xA0000 to 0xB0000
STPC CONSUMER-II
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