STPCC4 STMicroelectronics, STPCC4 Datasheet - Page 39

• Manufacturer Part Number: STPCC4
• Description: STPC CONSUMER-II DATASHEET - X86 CORE PC COMPATIBLE INFORMATION APPLIANCE SYSTEM-ON-CHIP
• Manufacturer: STMicroelectronics

4.5.2 RESET SEQUENCE
Figure 4-4 describes the reset sequence of the
STPC, also called warm reset.
The constraints on the strap options and the bus
activities are the same as for the cold reset.
The SYSRSTI# pulse duration must be long
enough to have all the strap options stabilized and
must be adjusted depending on resistor values.
Figure 4-4. Reset timing diagram
1 4 M H z
S Y SR S TI#
ISA C L K
S tr a p O p tio n s
H C L K
P C I_ C L K
S Y SR S TO #
M D [6 3 :0 ]
Release 1.5 - January 29, 2002
1 .6 V
VA L ID C O N F IG U R A TIO N
It is mandatory to have a clean reset pulse without
glitches as the STPC could then sample invalid
strap option setting and enter into an umpredicta-
ble mode.
While SYSRSTI# is active, the PCI clock PLL runs
in open loop mode at a speed of few 100’s KHz.
ELECTRICAL SPECIFICATIONS
2 .3 m s
39/93