STPCC4 STMicroelectronics, STPCC4 Datasheet - Page 79

• Manufacturer Part Number: STPCC4
• Description: STPC CONSUMER-II DATASHEET - X86 CORE PC COMPATIBLE INFORMATION APPLIANCE SYSTEM-ON-CHIP
• Manufacturer: STMicroelectronics

memory clock input (MCLKI) and any other
component
individually driven from a low skew clock driver
with matched routing lengths. In other words, all
The maximum skew between pins for this part is
250ps. The important factors for the clock buffer
are a consistent drive strength and low skew
between the outputs. The delay through the buffer
is not important so it does not have to be a zero
delay PLL type buffer. The trace lengths from the
clock driver to the DIMM CKn pins should be
matched exactly. Since the propagation speed
can vary between PCB layers, the clocks should
be routed in a consistent way. The routing to the
STPC memory input should be longer by 75 mm to
compensate for the extra clock routing on the
* No additional 75mm when SDRAM directly soldered on board
Low skew clock driver:
using
MCLKO
the
memory
Figure 6-19. DIMM placement
Figure 6-20. Clock Routing
Release 1.5 - January 29, 2002
clock
are
SDRAM I/F
DIMM2
DIMM1
116mm
STPC
35mm
clock line lengths that go from the buffer to the
memory chips (MCLKx) and from the buffer to the
STPC (MCLKI) must be identical.
This is shown in Figure 6-20.
DIMM. Also a 20 pF capacitor should be placed as
near as possible to the clock input of the STPC to
compensate for the DIMM’s higher clock load. The
impedance of the trace used for the clock routing
should be matched to the DIMM clock trace
impedance (60-75 ohms)
the clocks should be routed with spacing to
adjacent tracks of at least twice the clock trace
width. For designs which use SDRAMs directly
mounted on the motherboard PCB all the clock
trace lengths should be matched exactly.
L+75mm*
L
15mm
35mm
20pF
DIMM CKn input
DIMM CKn input
DIMM CKn input
10mm
DESIGN GUIDELINES
.
To minimise crosstalk
STPC MCLKI
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