LMH1983SQ/NOPB National Semiconductor, LMH1983SQ/NOPB Datasheet - Page 5

• Manufacturer Part Number: LMH1983SQ/NOPB
• Description: IC VID CLK GEN MULTI RATE 40LLP
• Manufacturer: National Semiconductor
• Type: Clock Generatorr

Specifications of LMH1983SQ/NOPB

• Applications: Video Equipment
• Mounting Type: Surface Mount
• Package / Case: 40-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Notes
1. The NO_LOCK status flag is derived from the Lock Status register bits (LOCK1-4) for each PLL. Each lock status bit can be masked from the NO_LOCK flag
by setting their respective mask bits.
2. SDA and SCL pins each require a pull-up resistor of 4.7 kΩ to the VDD supply.
3. XOin must be driven by a 27 MHz clock in order to read or write registers via I
Pin No.
30
31
32
33
34
35
36
37
38
39
40
Pin Name
CLKout1–
CLKout1+
VC_LPF
XOin–
XOin+
Fout2
Fout1
GND
VDD
VDD
VDD
I/O
O
O
O
O
–
–
–
–
I
LVCMOS/LVDS 27 MHz VCXO clock signal for PLL1.
Signal Level
LVCMOS
LVCMOS
Analog
Power
Power
Power
LVDS
GND
5
Video frame timing signal for OUT2 (active low). Timing generator
assignable to PLL1, PLL2, or PLL3. OUT2 format is selectable
via the host.
3.3V supply for CLKout2
3.3V supply for PLL2
– LVCMOS: Directly connect clock signal to XOin+ and bias
XOin- to mid-supply with 0.1uF bypass capacitor.
– LVDS: Directly connect LVDS clock signals to XOin+ and XOin-.
Note: A TCXO or other clean 27 MHz oscillator can be applied
for standalone clock generation using PLLs 2-4 (bypass PLL1).
Video clock from PLL1.
The output is 27 MHz by default and is selectable via the host.
Reference frame timing signal for OUT1 (active Low). Timing
generator fixed to PLL1 OUT1 Format follows the reference input
format.
3.3V supply for CLKout1
Ground
Loop filter for PLL1 charge pump output with VCXO Voltage
Control (VC) sensing.
If free-run and holdover mode, PLL1 is disabled and an internal
DAC outputs a control voltage to the VCXO.
2
C.
Pin Description
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