LMH1983SQ/NOPB National Semiconductor, LMH1983SQ/NOPB Datasheet - Page 29

• Manufacturer Part Number: LMH1983SQ/NOPB
• Description: IC VID CLK GEN MULTI RATE 40LLP
• Manufacturer: National Semiconductor
• Type: Clock Generatorr

Specifications of LMH1983SQ/NOPB

• Applications: Video Equipment
• Mounting Type: Surface Mount
• Package / Case: 40-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CLK4, and a 5.996 Hz output from TOF4. This is done by
taking CLK1 (27 MHz), and dividing it by 75, resulting in a
signal of 360 kHz, this is compared to the internal PLL4 VCO,
which is nominally 1.2 GHz, divided by 4096, which again
yields 360 kHz. This 1.2 GHz output is divided by 12 to gen-
erate a 98.304 MHz signal (48 kHz * 2048). Any power of two
multiple of 48 kHz can be generated by changing the contents
of the PLL4_DIV component of register 0x34. Note that the
divider here is in powers of 2, so the default value of 2, results
in the 98.304 MHz signal being divided by 2
is a 4 bit value, so values up to 15 may be programmed, re-
sulting in a divide by 2
If audio clocks based on a 44.1 kHz sampling clock are de-
sired, refer to applications note AN–2108 available on the
Clock Output Jitter
Several of the circuits which require video clocks, such as the
embedded Serializers and Deserializers found in FPGAs are
sensitive to jitter. In all real world applications, jitter has a ran-
dom component, so it is best specified in statistical terms. The
SMPTE serial standards (SMPTE 259M, SMPTE 292M and
SMPTE 424M) use a frequency domain method of specifying
jitter in which they refer to the peak-to-peak jitter of a signal
after the jitter has been band pass filtered. Jitter at frequen-
cies below 10 Hz is ignored, and the jitter in a band from 10
Hz to an intermediate frequency (1 kHz for the 270 Mbps
standard, 100 kHz for the 1.5 Gbps and 3 Gbps standards) is
referred to as timing jitter, jitter from the intermediate frequen-
cy up to 1/10 of the serial rate is referred to as alignment jitter.
The limits that the SMPTE standards place are peak-to-peak
limits, but especially at the higher rates, random processes
have a significant impact, and it is not possible to talk about
peak-to-peak jitter without a corresponding confidence level.
The methodology used to specify the jitter on the LMH1983
was to decompose the jitter into a deterministic component
(t
used by the jitter analysis tools supported on high bandwidth
DJ
) plus a random component (t
15
or 32,768.
RJ
). This is the methodology
2
or 4. PLL4_DIV
PLL4 Block Diagram
29
National Semiconductor web site for detailed instructions on
how to set up the appropriate register settings to generate
44.1 kHz audio clocks.
TOF4 has two different modes in which it can operate. When
the AFS_mode bit (in register 0x09) is set to a 0, then TOF4
is derived by dividing down CLKout4 by a value of
2
then TOF4 is derived from TOF1 — divided by AFS_div (reg-
ister 0x49). When AutoFormatDetect is true, then the
AFS_div register is read only, and is internally set depending
upon the format detected.
oscilloscopes and timing analysis tools from the major instru-
mentation manufacturers.
To convert between RMS jitter and peak-to-peak jitter the Bit
Error Rate (BER) must be specified. Without a known BER,
since jitter is a random event, the peak-to-peak jitter will be
dependent upon the observation time, and can be arbitrarily
large. The equation which links peak to peak jitter to the RMS
jitter is:
Where α is determined by the BER according to the equation:
The erfc (error function) function can be found in several
mathematics references, and is also a function in both Excel
and MATLAB. A fairly common BER used for these calcula-
tions is 10
Another common method for evaluating the jitter of a clock
output is to look at the phase noise, as a function of frequency.
Plots showing the phase noise for each of the four CLKout
outputs can be found below.
TOF4_ACLK
-12
(register 0x4A). if the AFS_mode bit is set to a 1,
, which can be used to find a value of 14 for α.
1/2erfc(
t
P-P
= t
√
DJ
2*α) = BER
+α*t
RJ
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