LMH1983SQ/NOPB National Semiconductor, LMH1983SQ/NOPB Datasheet - Page 11

• Manufacturer Part Number: LMH1983SQ/NOPB
• Description: IC VID CLK GEN MULTI RATE 40LLP
• Manufacturer: National Semiconductor
• Type: Clock Generatorr

Specifications of LMH1983SQ/NOPB

• Applications: Video Equipment
• Mounting Type: Surface Mount
• Package / Case: 40-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Descriptions
The following table provides details on the device's configuration registers. Default value for fields 7 bits and less are expressed
in binary, default values for fields that are 8 bits (Byte) are expressed in hex. Do not write to Reserved (RSVD) fields.
Register Map
ADD
0x00
0x01
0x02
0x03
0x04
Name
Device Status
— Input Reference
Device Status
PLL Lock and Output
Alignment Status
Revision ID
Reserved
Bits
7
6
5
4
3
2
1
0
7
6
5
4
3:0
7:4
3:0
7:0
7:0
Field
INTERLACED
ANALOG_REF
INPUT_POLARITY
HSYNC_STATUS
H_ONLY
LOR_STATUS
LOST_HSYNC
Reserved
Lock_Status
Align_Status
Wrong_Format
Holdover
RSVD
Lock_Detect
Align_Detect
RSVD
11
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Default
—
—
—
—
—
—
—
—
1
0
1
0
–
–
0xC0
Description
Indicates if the input reference format is an
interlaced format
This bit is set depending on if the sync
detection circuit had determined if the
reference is an analog or digital derived
signal
Returns the value of the input polarity
determined by the sync detector for HSYNC
— 0 indicates an active low sync
This bit is set if the Hsync During Vsync
detector will set NO_H_DURING_V on the
next rising edge of VSYNC
This is set by the Interlaced detector
Returns the inverse of the NO_REF output
pin state
Set if HSYNC_MISSING is high wile
no_h_during_v is low. Remains set until
read, then self-clears
Reserved — always returns '0'
Returns lock status for all unmasked and
enabled PLLs
Returns the Align Status for all enabled TOFs
Returns the value of the Wrong_Format bit.
Returns the value of the PLL Holdover Bit
Reserved
[7] indicates the lock status of PLL4.
[6] indicates the lock status of PLL3.
[5] indicates the lock status of PLL2.
[4] indicates the lock status of PLL1.
0 = PLL Not Locked
1 = PLL Locked
[3] indicates the lock status of TOF4.
[2] indicates the lock status of TOF3.
[1] indicates the lock status of TOF2.
[0] indicates the lock status of TOF1.
0 = TOF Alignment not detected
1 = TOF alignment detected
Returns device revision code
Reserved
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